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| sensille | i tried to build the colorlite project, https://github.com/enjoy-digital/colorlite, but it fails timing: 44.83 MHz (FAIL at 50.00 MHz) and 110.78 MHz (FAIL at 125.00 MHz). is anyone here using it? | 11:12 |
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| _florent_ | Hi sensille, the timing were indeed a bit off, but some improvements have been done recently to use a 32-bit datapath in the Ethernet core, which improves timings, not sure this is already applied to ColorLite project (I created it as simple demo and use it BTW). | 15:13 |
| _florent_ | It also seems that some developers are building a CNC controller using it as a basis: https://forum.linuxcnc.org/27-driver-boards/44422-colorcnc | 15:14 |
| tpb | Title: ColorCNC Colorlight 5A-75E/5A-75B as FPGA controller board - LinuxCNC (at forum.linuxcnc.org) | 15:14 |
| _florent_ | you can probably find some useful information there too | 15:14 |
| sensille | i installed litex only a few days ago, should the improvements be automatically included in colorlite? | 15:15 |
| sensille | the project is what brought me here :) | 15:15 |
| sensille | i built that and noticed the failed timing. to simplify things i tried colorlite next, with the same result | 15:16 |
| sensille | it also highly depends on the yosys/nextpnr version | 15:16 |
| sensille | i'm trying to wrap my head around litex, so i can contribute to the cnc project :) | 15:16 |
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| sensille | the basic idea of litex is quite tempting, i have a variety of boards supported by litex | 15:18 |
| sensille | is there a central module documentation, or is the source code the documentation? | 15:21 |
| _florent_ | I would recommend exploring the Wiki: https://github.com/enjoy-digital/litex/wiki | 15:36 |
| _florent_ | and the slides: https://docs.google.com/presentation/d/1mQOWqgmyQxpjLAzFwCulqgkp0TuxmaIDYp5iUfPqqIk/edit | 15:37 |
| tpb | Title: LiteX: SoC builder framework - Google Präsentationen (at docs.google.com) | 15:37 |
| _florent_ | documentation is still sparse but we are trying to improve it progressively | 15:37 |
| sensille | but i slowly start to get the idea :-) | 15:52 |
| sensille | another thing i noticed is that litex_sim doesn't work with a recent version of verilator, probably due to the change in the interface with verilator 4.210 | 16:10 |
| sensille | and one more: for the rv901t colorlight board (spartan 6, ISE 14.7), ISE optimizes eth_tx_clk away, so that the .ucf is wrong | 17:52 |
| _florent_ | can you fill an issue for Verilator? Because I just recompiled verilator a few days ago and litex_sim was working | 18:03 |
| _florent_ | For spartan6, I indeed spend minimal time getting things working since I no longer use ISE that much, but things were compiling IIRC, if it's no the case, please also fill an issue, I'll have a look. I remember fixing something similar | 18:04 |
| sensille | strange. i was using a recent oss_cad_suite and got some errors. when i double checked with a version for 20210706 it worked | 18:05 |
| sensille | i seems like i can just constrain on eth_rx_clk instead | 18:05 |
| sensille | unfortunately vivado does not support spartan 6 | 18:08 |
| sensille | issue for eth_tx_clk opened. i will double check the litex_sim issue before creating an issue for that | 18:20 |
| sensille | wohoo, it pings! :-) | 18:52 |
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