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| mewt | Thanks. Interestingly, that appears to produce no output at all | 00:30 |
|---|---|---|
| tpw_rules | i think you have to give it/maybe it writes to a default file path | 00:31 |
| mewt | I mean, I've searched my entire filesystem for the name | 00:36 |
| mewt | should it generate a blank file if by some strange misconfiguration there are no CSRs? | 00:40 |
| mewt | I guess I'll try and figure out from the source tomorrow | 00:41 |
| somlo | mewt: try something like `litex-boards/litex_boars/targets/digilent_nexys_video.py --build --cpu-type rocket --cpu-variant full4d --sys-clk-freq 50e6 --csr-csv ./foo.csv` | 01:22 |
| somlo | substitute your own board, cpu type, variant, frequency, etc. | 01:23 |
| somlo | but MMIO register addresses should be dumped into the `foo.csv` file | 01:23 |
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| mewt | Yeah, works even without that target finishing | 05:03 |
| mewt | So I guess this is somehow the fault of colorlight_i5.py | 05:03 |
| mewt | It is because it's not built by default, and now this thing appears to have some issue if you set CSR widths <32 | 05:35 |
| mewt | apparently what fails is "master_rxtx", which appears to not be part of any peripheral core. Somehow the width of that remains as 32 bits, which causes it to fail an assert (that every CSR is 8 bits or less) | 05:44 |
| mewt | At least that's my understanding right now playing with the debugger | 05:45 |
| mewt | I would like to get litex to actually build something for the colorlight i5 again, but it seems recent versions of the toolchain both on this and the zephyr side have changed too much and things in colorlight_i5.py need updating | 05:51 |
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| mewt | Ah nope this is part of the SPI master for spi flash I think | 06:38 |
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| _florent_ | mewt: can you share a command to reproduce the issue? | 08:11 |
| _florent_ | Just for info, with: https://github.com/enjoy-digital/litex/commit/3603e90ed8de1f3863524049e67dea710c97112f we can now directly create CSRs on the main module of a SoC. These ones will be collected and added to a "main" submodule with all the CSR attached to it. This can be convenient when debugging a SoC to quickly add registers or logic to help debug without having to create a specific submodule. | 08:18 |
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| mewt | from targets directory: colorlight_i5.py --with-sdcard --with-ethernet --integrated-rom-size 0xc000│179 program_cmd) | 14:21 |
| mewt | ... | 14:21 |
| mewt | Sorry, one moment | 14:22 |
| mewt | ./colorlight_i5.py --with-sdcard --with-ethernet --integrated-rom-size 0xc000 --l2-size 2048 --csr-data-width 8 --build --csr-csv='./soc.csv' | 14:23 |
| mewt | should bail during the build step, on an assertion that "master_rxtx" is 8 bits or less | 14:31 |
| mewt | (you will have to use pdb or modify the code to see that name) | 14:31 |
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| _florent_ | mewt: OK thanks, this seems to be a limiation of LiteSPI with csr_data_width of 8. I'll try to have a closer look | 17:57 |
| mewt | Thank you! | 18:23 |
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