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| _florent_ | somlo: The aim of these changes is to allow fixed mapping of the register offsets and one use case are the linux drivers. | 06:48 |
|---|---|---|
| _florent_ | somlo: LiteEth is collecting the CSR differently and this case does not seems to be covered correctly, I'll fix this, sorry for that. | 06:49 |
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| _florent_ | somlo: This is good now (compared the generated mappings with your example) | 07:26 |
| DerekKozel[m] | Thanks for this feature | 08:11 |
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| _florent_ | DerekKozel[m]: This was required for quite some time :) (and isn't finished), next I'll prepare the design we were discussing for you GnuRadio tests. | 09:23 |
| _florent_ | you/your | 09:23 |
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| somlo | _florent_: thanks, it looks fine now (getting the same offsets as before) | 13:24 |
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| _florent_ | DerekKozel[m]: An example of minimal ComputeEngine for a LitePCIe design: https://github.com/enjoy-digital/acorn_pcie_compute_test/commit/b226ccad7049f71ef4485a256ea78703f82500c7 | 20:15 |
| _florent_ | DerekKozel[m]: And how to pipeline engines: https://github.com/enjoy-digital/acorn_pcie_compute_test/commit/6da15709ff7f93b3f6a19b9a53eb877baec262a7 | 20:15 |
| _florent_ | DerekKozel[m]: With this, you can use litepcie_test play to inject data and litepcie_test record to get back the modified data | 20:18 |
| _florent_ | DerekKozel[m]: So you can pipeline different engines on the same DMA | 20:18 |
| _florent_ | DerekKozel[m]: but can also have several independant DMAs, each with its own processing pipeline | 20:19 |
| _florent_ | DerekKozel[m]: To configure the number of DMAs in the design: you can use the ndmas of add_pcie | 20:20 |
| _florent_ | DerekKozel[m]: and you can select the DMA with litepcie_test with -c X | 20:20 |
| _florent_ | DerekKozel[m]: In the ComputeEngine, the sink/source endpoint are LiteX streams which are very similar to AXI stream | 20:21 |
| _florent_ | https://github.com/enjoy-digital/litex/wiki/Streams | 20:22 |
| _florent_ | Derivating from stream.PipelinedActor avoid having to handle the control signals manually (valid/ready), you can just focus on the data processing. | 20:24 |
| DerekKozel[m] | Excellent | 20:35 |
| DerekKozel[m] | The Pipeline class/concept I had missed before, that is ideal and so simple. I'll get that running and building dynamically. | 20:37 |
| DerekKozel[m] | Thank you | 20:37 |
| DerekKozel[m] | I can easily stay busy for a week or two with this example. Registers and Verilog will be the two most useful things after that. | 20:39 |
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