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| cr1901_ | _florent_: Would you support an addition to LiteX to make a "crossbar bus, but not every peripheral is accessible by every master" (multimaster design)? | 01:03 |
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| cr1901 | (alternate solution is to gate wishbone CYC directly at each master, deasserting if the address isn't in range. But I'd prefer not relying on the optimizer to prove that logic can just plain be removed.) | 02:12 |
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| _florent_ | cr1901: I'm planning to support more bus topologies in the future yes, for now things are very simple in the LiteX integration, more complex are already possible but have to be done manually. | 11:20 |
| _florent_ | cr1901: the best would be to experiment your idea with manual instance if the interconnect/peripherals/etc... and we could then see if this is possible to merge it or better to wait a bit | 11:21 |
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