Thursday, 2022-07-14

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jevinskie[m]Weird, I keep getting simulated etherbone timeouts where after a burst of r/w one of the reads never responds with a packet. This is with iverilog and Questa, a similar thing happened when I modified the Ethernet module to work with macOS where libevent had to block on tap reads…01:04
jevinskie[m]I switched over to uartbone over serial2tcp and that seems to fix or paper over the issue. Just required a small superclass of CommUART to make a socket connection01:05
jevinskie[m]Anybody else see suspicious litescope timeouts?01:05
jevinskie[m]I wonder if the Ethernet simulation is too slow while the uart PHY is much more lightweight?01:06
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cr1901trabucayre: Sorry, I'm not going to get to testing your gist tonight. I'll do it when I wake up tomorrow03:51
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trabucayrecr1901: no problems05:11
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cr1901trabucayre: https://github.com/trabucayre/openFPGALoader/issues/230#issuecomment-118468426717:09
trabucayreanswered :)17:17
cr1901trabucayre: I got an LA trace for you17:31
cr1901Wait... I might've screwed up the duration, hold on17:32
trabucayreit's maybe not the right location to talk about that :)17:34
cr1901Is there an openFPGALoader IRC channel?17:35
cr1901trabucayre: If no IRC channel, you may wish to idle in ##openfpga. openFPGALoader is on topic there by being an "Open source tool for FPGAs/JTAG"17:41
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trabucayreI have to create one yep19:28

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