| *** tpb <[email protected]> has joined #litex | 00:00 | |
| *** Degi_ <[email protected]> has joined #litex | 02:25 | |
| *** Degi <[email protected]> has quit IRC (Ping timeout: 255 seconds) | 02:25 | |
| *** Degi_ is now known as Degi | 02:25 | |
| *** dklim <[email protected]> has joined #litex | 06:57 | |
| *** dklim <[email protected]> has quit IRC (Ping timeout: 268 seconds) | 07:02 | |
| *** esteves <[email protected]> has joined #litex | 12:03 | |
| *** indy <[email protected]> has quit IRC (Ping timeout: 256 seconds) | 12:08 | |
| *** esteves <[email protected]> has quit IRC (Quit: Client closed) | 12:11 | |
| *** indy <[email protected]> has joined #litex | 12:13 | |
| *** xenador77 <xenador77!~xenador77@user/xenador77> has joined #litex | 12:57 | |
| lambda | how does migen convert nested python submodules to flat verilog identifiers? I can't really find a pattern for when it inserts the module name into the signal name and when it doesn't | 12:58 |
|---|---|---|
| lambda | does it just try to use the signal names as-is, and prepend module names whenever there are collisions? | 13:02 |
| lambda | are there any known issues with this renaming? I'm trying to figure out why there's a logic loop in the generated verilog, and it's quite hard to associate the signal names with their corresponding python code, sometimes it feels like multiple Signals got the same verilog signal name or something | 13:26 |
| lambda | nevermind, looks like it was just a good old logic bug. | 13:46 |
| *** xenador77 <xenador77!~xenador77@user/xenador77> has quit IRC (Remote host closed the connection) | 15:05 | |
| *** xenador77 <xenador77!~xenador77@user/xenador77> has joined #litex | 15:06 | |
| *** smosanu <[email protected]> has joined #litex | 15:10 | |
| smosanu | mithro (or anyone else) please feel free to reach out to me with any questions regarding the PiMulator paper/platform | 15:11 |
| *** smosanu <[email protected]> has quit IRC (Quit: Client closed) | 15:33 | |
| jevinskie[m] | The Cologne Chip rep got back to me and mentioned others are already evaluating them for use with LiteX :) | 16:52 |
| trabucayre | jevinskie[m]: yep : me :) | 17:00 |
| trabucayre | https://github.com/trabucayre/litex/tree/colognechip | 17:01 |
| trabucayre | https://github.com/trabucayre/litex-boards/tree/gatemate_evb | 17:01 |
| trabucayre | but it's requires a patch for yosys and without CPU :( | 17:01 |
| trabucayre | I have to search why :) | 17:01 |
| *** xenador77 <xenador77!~xenador77@user/xenador77> has quit IRC (Remote host closed the connection) | 17:29 | |
| *** xenador77 <xenador77!~xenador77@user/xenador77> has joined #litex | 17:30 | |
| *** xenador77 <xenador77!~xenador77@user/xenador77> has quit IRC (Remote host closed the connection) | 17:39 | |
| *** xenador77 <xenador77!~xenador77@user/xenador77> has joined #litex | 17:40 | |
| *** smosanu <[email protected]> has joined #litex | 20:32 | |
| *** smosanu <[email protected]> has quit IRC (Quit: Client closed) | 20:50 | |
| *** xenador77 <xenador77!~xenador77@user/xenador77> has quit IRC (Remote host closed the connection) | 21:11 | |
| *** xenador77 <xenador77!~xenador77@user/xenador77> has joined #litex | 21:11 | |
| *** anuejn <[email protected]> has quit IRC (Remote host closed the connection) | 21:34 | |
| *** anuejn <[email protected]> has joined #litex | 21:35 | |
| *** Melkhior <Melkhior!~Melkhior@2a01:e0a:1b7:12a0:225:90ff:fefb:e717> has quit IRC (Read error: Connection reset by peer) | 21:38 | |
| *** Melkhior <Melkhior!~Melkhior@2a01:e0a:1b7:12a0:225:90ff:fefb:e717> has joined #litex | 21:39 | |
| jevinskie[m] | So it looks like, to support existing modules in VPI, I have two options 1) add signal getter/setters (for Verilator: pointer derefs, for VPI: vpi_get_value/vpi_put_value 2) emulate the Vsim object by scanning out signals at the start of the timestep and writing the stub Vsim values out at the end | 22:18 |
| jevinskie[m] | I'll go with 2 for now since it seems to be the simplest but it might have some performance overhead | 22:19 |
| *** shorne <[email protected]> has quit IRC (Remote host closed the connection) | 22:52 | |
| *** shorne <[email protected]> has joined #litex | 22:57 | |
| *** shorne <[email protected]> has quit IRC (Client Quit) | 22:58 | |
| *** shorne <[email protected]> has joined #litex | 22:58 | |
| *** xenador77 <xenador77!~xenador77@user/xenador77> has quit IRC (Remote host closed the connection) | 23:26 | |
| *** xenador77 <xenador77!~xenador77@user/xenador77> has joined #litex | 23:26 | |
| *** xenador77 <xenador77!~xenador77@user/xenador77> has quit IRC (Ping timeout: 252 seconds) | 23:47 | |
Generated by irclog2html.py 2.17.2 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!