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| _florent_ | jevinskie[m]: this would be interesting to explore it yes. | 07:06 |
|---|---|---|
| _florent_ | jevinskie[m]: BTW, regarding QOI, amstan here was experimenting with it on FPGA: https://libera.irclog.whitequark.org/litex/2022-04-24#32138207 | 07:07 |
| tpb | Title: #litex on 2022-04-24 — irc logs at libera.irclog.whitequark.org (at libera.irclog.whitequark.org) | 07:07 |
| _florent_ | jevinskie[m]: https://github.com/amstan/qoi-fpga | 07:07 |
| _florent_ | I was also curious to experiment with it but haven't found the time yet | 07:08 |
| amstan | yeah, i need to get on that still | 07:09 |
| amstan | i actually found someone even made an ip block you can buy for it, with a datasheet and everything | 07:09 |
| amstan | api looked very similar to mine | 07:10 |
| _florent_ | jevinskie[m]: I would also be very interested to see what results it gives for LiteScope captures | 07:10 |
| amstan | https://www.xilinx.com/products/intellectual-property/1-1o2l4ko.html#overview | 07:10 |
| amstan | so formal, why can't it be open source? | 07:10 |
| amstan | i guess that's where things like litex will come in | 07:11 |
| _florent_ | amstan: Having an open-source implementation for QOI is indeed a lot more interesting | 07:12 |
| _florent_ | amstan: We can help you doing the integration and prepare some tests on hardware | 07:13 |
| _florent_ | amstan: Can you remember how you were planning to test it? | 07:13 |
| amstan | the big piece that's missing right now is some kind of standard memory bus interface | 07:14 |
| amstan | i'm doing some tests with verilator where i took apart the software implementation and replaced the inner loop with a verilator simulation of a clock cycle | 07:15 |
| _florent_ | amstan: I could prepare some simulation/simple design to be able to do DRAM -> DMA -> QOI Decoder -> VideoOut and then full the DRAM with encoded QOI frames from the SDCard or from Ethernet | 07:21 |
| _florent_ | full the/fill the | 07:22 |
| amstan | that would be cool | 07:22 |
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| betocool | Question... what's the difference between Migen and nMigen? And which one does Litex use? | 08:04 |
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| pepijndevos[m] | LiteX uses Migen | 08:39 |
| pepijndevos[m] | nMigen is now Amaranth | 08:39 |
| pepijndevos[m] | It improves a few things about Migen, but is not backwards compatible. | 08:39 |
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| somlo | speaking of Migen -- it needs some help keeping up with Python 3.11 (https://github.com/m-labs/migen/issues/259), in case there are any Python experts hanging around | 12:55 |
| somlo | it's a bit deeper python magic than I'm equipped to deal with at short notice :) | 12:56 |
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| esteves | Hello, I need to add a fez constraints in the sdc file. To do that I'm using "platform.toolchain.additional_sdc_commands", is there a more elegant way to do this? (set_input_delay and set_output_delay commands) | 14:19 |
| esteves | few* | 14:20 |
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| jevinskie[m] | <amstan> "i actually found someone even..." <- For QOI, already? Hard to believe someone already tried to commercialize a hobby YOLO algorithm but I guess it’s performance is so compelling. | 17:19 |
| jevinskie[m] | <somlo> "it's a bit deeper python magic..." <- I can take a look :) | 17:21 |
| jevinskie[m] | <esteves> "Hello, I need to add a fez..." <- That’s the way to do it, you can wrap the appending in a helper function to make it prettier | 17:21 |
| somlo | jevinskie[m]: thanks, LMK what you find | 18:05 |
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| YehorKrapovnytsk | Hey, I wanna carry out the first lab from litex-hub and when I execute os.system("djtgcfg prog -d Nexys4DDR -i 0 -f ./build/top.bit") to program the device I get that djtgcfg not found. I googled a little and have found that I need Digilent Adept tool. It wasn't installed with litex. Ami right that I need to install it manually? | 18:51 |
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| esteves | ok, thank you. | 22:09 |
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| jevinskie[m] | This is interesting https://arxiv.org/abs/2101.05329 | 23:15 |
| tpb | Title: [2101.05329] Improving Run Length Encoding by Preprocessing (at arxiv.org) | 23:15 |
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