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| acathla | _florent_, i've got another problem... you removed LTO option from CFLAGS (-flto) in a commit, but I can't build my code anymore without adding it. Bios is building fine, what a I missing? | 11:51 |
|---|---|---|
| acathla | It fails with an error like : helpers.o: in function `command_dispatcher': [..]litex/soc/software/bios/helpers.c:125: undefined reference to `__bios_init_start' | 11:54 |
| pepijndevos[m] | uh oh... | 12:11 |
| pepijndevos[m] | what if I want more than 32 PWM controllers? | 12:11 |
| pepijndevos[m] | ERROR:SoCCSRHandler:Not enough Locations. | 12:12 |
| pepijndevos[m] | ERROR:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations). | 12:12 |
| pepijndevos[m] | I want uhh 32 PWMs and 16 stepper motor drivers plus some misc ethernet stuff | 12:14 |
| acathla | pepijndevos[m], add another PWM instance? | 12:19 |
| acathla | _florent_, if I do add -flto it builds, but prints strange things and mem_test reports errors | 12:20 |
| pepijndevos[m] | hmm seems like I just need to increas the csr address width maybe | 12:21 |
| pepijndevos[m] | 64 elements should be just about enough I think | 12:22 |
| _florent_ | pepijndevos[m]: you can indeed increase csr_address_width for this (we should maybe handle this automatically) | 12:41 |
| _florent_ | acathla: You probably only need to do a clean build of your software, as it is now done automatically by LiteX for the BIOS when CPU/build parameters are changed. | 13:01 |
| acathla | _florent_, I do that automatically too, it does not build... May be a bad usage of gnu-ar... | 13:41 |
| acathla | _florent_, found the bug, there is a new section in linker.ld : .init | 14:47 |
| pepijndevos[m] | hrm! what would be the most effective way to debug a vhdl peripheral? I simulated it by itself, and it appears to work fine, but when wrapped in litex auocsr stuff there is no output on the fpga | 14:57 |
| tnt | no output ? | 14:59 |
| tnt | And no warning during build ? | 15:00 |
| _florent_ | pepijndevos[m]: if it can be converted to verilog through GHDL or GHDL+Yosys, the most effective way to debug is probably to integrate it in a Verilator simulation and use Display (printf equivalent for logic) or look at the waveforms | 15:10 |
| pepijndevos[m] | yea i synth to verilog | 15:10 |
| pepijndevos[m] | so you'd synthesize the entire litex design in verilator? | 15:11 |
| _florent_ | a minimal Verilator sim with LiteX: https://github.com/enjoy-digital/litex_verilog_axi_test/commit/30054ee19fa58a1a480e0d9697ee56f5bcb46a35 | 15:11 |
| _florent_ | this simulates a minimal SoC (CPU + peripherals) | 15:11 |
| _florent_ | you can then add your peripherals to it, ex: https://github.com/enjoy-digital/litex_verilog_axi_test/commit/436b76b3f74a8c30fc5ff295d3685a4503d2f4ed#diff-63ed1180e575e50e2ac7d9314b969a38b038d90c16c76b3fb0b192f022c7d775 | 15:12 |
| pepijndevos[m] | ohhh | 15:13 |
| _florent_ | then you do "printf style" debug on output of your modules, ex: https://github.com/enjoy-digital/litex_verilog_axi_test/blob/0a752cffa3a5934812c91f3f3eb23d8865d498ec/verilog_axi/axi_common.py#L44-L87 | 15:14 |
| _florent_ | and with the LiteX BIOS, just access your peripheral through mem_write/mem_read and observe things | 15:15 |
| _florent_ | or you can also just modify the LiteX BIOS, load your ROM binary and look at the waveform, this will give you more visibility, but you have to search things in the waveform while Display just display the information you want. | 15:16 |
| pepijndevos[m] | meanwhile i was trying to bring out some debug signals on the actual fpga, but when I do that I get `ERROR: Cell port colorlight_5a_75b.stepper.step_out is driving constant bits: 1'0 <= \stepper.step_out` so that seems fishy | 15:25 |
| _florent_ | pepijndevos[m]: hmm, indeed, it seems your module is simplified, so probably an issue on the instance. | 15:28 |
| pepijndevos[m] | what do you mean? | 15:28 |
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| pepijndevos[m] | Can I display stuff directly from verilog/vhdl? | 15:49 |
| _florent_ | display is support in verilog, not sure in vhdl (or not sure if GHDL would convert vhdl equivalent to display) | 15:54 |
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| pepijndevos[m] | hmmm | 16:09 |
| pepijndevos[m] | how do I figure out the csr for the sim thing? It doesn't accept --csr-csv my.csv | 16:09 |
| pepijndevos[m] | so I can mem_write to the thing | 16:09 |
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| pepijndevos[m] | I just did the math in my head now... | 16:19 |
| pepijndevos[m] | it actually works perfectly in the simulator | 16:20 |
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| pepijndevos[m] | This one works perfectly: https://github.com/pepijndevos/rust-litex-example/blob/colorlight/simsoc.py... (full message at https://libera.ems.host/_matrix/media/r0/download/libera.chat/f991d87af0a7985034fe77f14942edb83a43a2e2) | 16:44 |
| pepijndevos[m] | This should do the same thing, but doesn't output anything: https://github.com/pepijndevos/rust-litex-example/blob/b3d80560863031786e1032d9c415ba4d719a56c0/colorlight_5a_75x.py#L182-L216 | 16:44 |
| pepijndevos[m] | Am I doing anything obviously wrong with how I hook things up? The Modegen and PWM blocks do work as expected, but the Stepper modules don't output anything. | 16:46 |
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| pepijndevos[m] | It's just completely weird. I can see the mode signal works. I can see the PWM signals on the same header. And it works in simulation. So it seems like everything is functional and hooked up correctly, but then there is just no output. | 17:15 |
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| joseng | Hey, after a long time not playing with Litex, I ran "litex_sim --with-etherbone", can ping the 192.168.1.51 and connect with "litex_server --udp --udp-ip 192.168.1.51". But when I try to run "litex_cli --regs", I get only timeout errors. | 20:46 |
| joseng | All runs on a Laptop with Ubuntu 22.04. Some rare times, I get the register content successfully. When I use --gui, I see the registers, but no values and also a timeout after some seconds | 20:48 |
| joseng | Is there anything else I can test to get why this is happening? | 20:49 |
| joseng | The ping times are below 1ms. When I run the udp scan with "litex_server --udp --udp-ip=192.168.1.x --udp-scan" multiple times, I get 75% of the runs no result | 20:51 |
| jevinskie[m] | I made a few quality of life improvements: add verbose mode to sw and sim compile, suppress verilator and verilator module warnings, and the ability to only build sw once when running the sim. I’ll polish them up and post PRs for them once I get some time. https://github.com/jevinskie/litex/commits/jev/usbstream-usbbone/main | 21:59 |
| jevinskie[m] | pepijndevos: sounds like it might be time to use litescope on the fpga (it works in simulator too over virtual Ethernet) https://github.com/enjoy-digital/litescope/blob/master/examples/arty.py | 22:03 |
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| jevinskie[m] | joseng: I had timeout issues with the verilator tap Ethernet modules. One thing that helped was increasing buffer lengths (sorry I forget which ones specifically) in Ethernet modules and the other was macOS specific where the tap driver doesn’t support events and I had to change the module to use reads with timeouts | 22:09 |
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