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| Hammdist | anyone know how to instantiate just the litex uart so I can include that as a module in my design? I don't want to generate a full SoC, but just the uart | 01:23 |
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| _florent_ | zyp: that would be great! | 05:10 |
| _florent_ | Otherwise, I'm trying to allocate some time to write doc, that's still parse but should improve progressively. | 05:11 |
| _florent_ | By collecting the different supports questions/answers (emails/github issues), it should already be possible to improve the doc without too much efforts. Then I should probably really block like some time in my agenda to write doc (sadly there are generally always other priorities...) | 05:16 |
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| swetland | I'm happy to do some review/feedback on doc stuff if that's useful (also I'll try to take some notes as I decipher things that maybe could turn into docs) | 05:27 |
| _florent_ | swetland: review/feedback is always useful yes (being familiar with the project, I no longer see some gaps in doc, etc...). Some notes of the difficulties you can have when adapting the code would also be useful (to know where to put the focus on for the doc). | 05:40 |
| _florent_ | mithro: thanks for the litex-hub profile page! | 05:40 |
| _florent_ | Hammdist: not exactly what you are looking for, but an example of JTAG-UART standalone core from LiteX components: | 05:47 |
| _florent_ | https://gist.github.com/enjoy-digital/0008ba45b1d517cebe2f4dbdb02753b0 | 05:47 |
| _florent_ | replacing the JTAGPHY with a UARTPHY could do what you want | 05:48 |
| _florent_ | Hammdist: or this: https://libera.irclog.whitequark.org/litex/2022-04-06#32048447; | 05:50 |
| tpb | Title: #litex on 2022-04-06 — irc logs at libera.irclog.whitequark.org (at libera.irclog.whitequark.org) | 05:50 |
| swetland | https://gist.github.com/swetland/1c6b0952647adf7565a8a81ad384d32c | 06:07 |
| swetland | some notes (maybe not correct!) on adding a second ethphy+ethmac to a board | 06:07 |
| swetland | I am still finding that depending on where I place the ethernet pmod I may or may not need the clock skew trick. Seems like a combination of gateware layout, baseboard trace lengths, and pmod trace lengths interacting, perhaps. I haven't fired up the fast scope to try to take pictures yet | 06:09 |
| _florent_ | swetland: thanks | 06:14 |
| swetland | this is one of those things where it'd be cool if the framework were a little more automatic (like it had the concept of peripheral instances so adding a second or third timer or gpio bank or whatever were a little more plug-and-play), but if not or until that, having some recipes/examples for how to do that might save folks time | 06:41 |
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| _florent_ | Playing a bit more with CoreScore, now 10 000 SERV CPUs on the VU19P: https://twitter.com/enjoy_digital/status/1530085417608957952 | 08:05 |
| _florent_ | the chip can do more since "only" 54% of the CLBs are used, but Vivado was crashing with 12 000 cores and 64GB of RAM, I would need to switch to 128GB (and switch to 32GB sticks) but not sure I have real need for this... | 08:08 |
| swetland | I am hoping that the next time I do work on xilinx parts I will be able to skip the Vivado experience... | 08:12 |
| swetland | Though last I checked all my makefiles and tcl scripts I use to drive their nonsense without using the UI still worked. So at least there's that. | 08:13 |
| _florent_ | swetland: When used in batch mode, I don't really have to complain that much about Vivado. It's sure slower than open-source toolchains on small designs but it scales well on large designs and once you are familiar with it you generally don't have that much surprises. | 08:19 |
| _florent_ | But the UI/BlockDesign/IP migration between versions is another thing yes... that I try to avoid | 08:20 |
| swetland | yeah their IP block stuff is pretty amazingly awful | 08:27 |
| swetland | It sounded neat when I first saw it, but it is so incredibly convoluted and ugly under the hood that it just is not worth dealing with | 08:28 |
| swetland | to the point where I ended up writing scripts to generate wrappers around the PS7's like 700 nets ^^ | 08:29 |
| swetland | (was doing MIPI2 CSI frontend stuff for machine vision on Zynq at the time. learned a lot about AXI 3 and 4) | 08:29 |
| leons | It's all nice when your system locale is set to English, but otherwise you're in for a treat | 08:30 |
| swetland | I can't even imagine | 08:30 |
| leons | Their weird tcl / java wizards generating XMLs with dots as decimal separators, but the actual synthesis engine expecting commas, etc... | 08:31 |
| swetland | oh no | 08:31 |
| swetland | I look at the house of cards of these vendor tools and you can see the eras of technology stack up... | 08:31 |
| swetland | like back in the day TCL was basically *the* scripting/automation language and everyone adopted it | 08:32 |
| swetland | and then in the early 2000s people started trying to overhaul their GUIs and got sold on Java and XML | 08:32 |
| swetland | but of course kept all the TCL for compatibility | 08:32 |
| swetland | and bolted in piles of native shared libs for performance | 08:33 |
| leons | I have already developed somewhat of a Stockholm syndrome when it comes to Vivado :) At least with that toolchain I have a rough idea where to punch it to get it to work ^^ | 08:33 |
| swetland | I'm sorta fearing a next generation where they keep ALL OF THAT and then wrap a new UI built on Electron/JS or Flutter/Dart on top of it, and bridge between JSON, XML, and TCL | 08:33 |
| swetland | what I'm *hoping* for is we'll eventually see the foss software stacks win out like they did in the C/C++ compiler arena | 08:34 |
| leons | For instance, just recently the gtwizard magically took care of automatic rerouting of a refclk input for me, but then set the clock selection to complete garbage. For these bugs their device view to look at the actual implemented design is actually quite nice :) | 08:35 |
| swetland | and have the vendors finally give up on trying to make the core toolchain the "value add" | 08:35 |
| swetland | oh I do like the visualization tools | 08:35 |
| leons | Sure, if they would have working wizards all of this wouldn't be needed, but eh | 08:35 |
| swetland | It's a lot easier to look at what vivado turned your verilog into than yosys/nextpnr | 08:36 |
| leons | Assuming it doesn't segfault, that is :) | 08:36 |
| swetland | well, vendor tools. if they worked all the time where would the adventure be? | 08:36 |
| leons | true | 08:37 |
| swetland | I wasted a day and a half doing bringup on a mcu/radio because the vendor only gives access to the radio via a blackbox library and you need to use their IDE/Wizard to configure it and generate a big 'ol slam table the radio_init() ingests | 08:37 |
| swetland | and I realized that I had started using their out of date IDE, so installed the new multi-GB monstrosity, and then everything went to shit | 08:38 |
| swetland | until I figured out that the importer for the radio config changed the part family (which is NOT VISIBLE ANYWHERE in the CONFIG UI) so it was generating a slam table for the wrong part | 08:38 |
| leons | uh, just realized the latest Vivado is an >70GB download. Not fit for German broadband... | 08:40 |
| swetland | swetland@dontpanic:~$ du -ks /work/app/* | sort -n | 08:46 |
| swetland | 34052 /work/app/yosys | 08:46 |
| swetland | 81552 /work/app/prjtrellis | 08:46 |
| swetland | 99776 /work/app/verilator | 08:46 |
| swetland | 112504 /work/app/icestorm | 08:46 |
| swetland | 530320 /work/app/nextpnr | 08:46 |
| swetland | not quite 3/4 GB! | 08:46 |
| swetland | or just over maybe (math is hard when I'm half alseep) | 08:47 |
| leons | smaller than Vivado for sure, not that that'd be hard to accomplish I suppose | 08:48 |
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| mithro | swetland: -H :-) | 18:08 |
| jevinskie[m] | Bah, I think I’m going to go down another rabbit hole and try to implement RLE for litescope - it would really be nice to get a dozen seconds worth of USB UTMI data instead of sub milliseconds :) anybody else need this and want to help? :) https://github.com/enjoy-digital/litescope/issues/7 | 18:11 |
| jevinskie[m] | Ah I have to go back to 2016 to find the original source https://github.com/enjoy-digital/litescope/blob/e211d17ca620c2c982a5a21996b577dbf04a2701/litescope/core/storage.py#L43 | 18:17 |
| Hammdist | VexRiscv generated by GenSmallestNoCsr seems to get stuck on an `sb` instruction. did I do something wrong or is it possible the core is so minimal it only supports word-sized memory access? | 20:17 |
| Hammdist | actually it gets stuck on the preceding `li` instruction .. now I'm stumped | 20:32 |
| swetland | what does that exactly disassemble to (is it maybe a constant load through a global register that's uninitialized?) | 20:35 |
| somlo | Hammdist, swetland: per google ("li riscv instruction") I found https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md#load-immediate | 20:40 |
| somlo | I'll go ahead and bookmark that for myself, should come in handy in the future :) | 20:40 |
| somlo | but `li` is an alias for a `lui` + `addi`, and does *not* touch any other register but the intended load target | 20:41 |
| swetland | it was my understanding that the assembler treats li as a pseudo op for "most efficient way to get the constant into the register" | 20:41 |
| swetland | so for small constants it could be just an addi target, x0, imm etc etc | 20:42 |
| somlo | which happens to be `lui` followed by `addi` if needed | 20:42 |
| swetland | per the RISCV Unprivileged ISA, li is an alias for "myriad sequences". I do agree that lui+addi or just addi seem most likely. | 20:44 |
| somlo | true, one can do an immediate load just by adding x0 to something... guess the only way to tell is to disassemble whatever is running (e.g. with objdump) | 20:44 |
| swetland | my instinct on "core is hanging on instruction at <addr>" is "check exactly what instruction that is" | 20:45 |
| Hammdist | 24: 04200693 li a3,66 | 21:20 |
| Hammdist | perhaps I didn't build a correct toolchain | 21:25 |
| swetland | that's addi a3, zero, 66... so certainly seems like the cpu should be plenty happy with it | 21:25 |
| swetland | nah, objdump helpfully disassembles addi target, zero, imm as a li to make it more human friendly | 21:25 |
| Hammdist | https://paste.ee/p/oHdpL | 21:26 |
| tpb | Title: Paste.ee - View paste oHdpL (at paste.ee) | 21:26 |
| Hammdist | notice how the last time iBus_cmd_valid is high is for fetching pc 0x24 | 21:27 |
| Hammdist | maybe the dBus didn't acknowledge correctly | 21:28 |
| swetland | 00d701a3 sb a3,3(a4) | 21:29 |
| Hammdist | that too but it's never actually requested by the cpu | 21:33 |
| * swetland nods | 21:34 | |
| Hammdist | indeed 04200693 somehow causes a dBus command that doesn't get acknowledged. I'm not clear on why it's causing a dBus command even but probably more digging will reveal the reason | 21:37 |
| Hammdist | ah it's from an instruction earlier in the pipeline | 21:45 |
| Hammdist | https://paste.ee/p/J9G7A ... don't understand why it's generating such complex code ... and why there is a load of the TXREG | 21:53 |
| tpb | Title: Paste.ee - View paste J9G7A (at paste.ee) | 21:53 |
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