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| shorne_ | swetland: I find understanding qemu command line arguments more difficult then the actual code for developing new hardware in qemu | 12:36 |
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| geertu | shorne_: +1 | 12:38 |
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| jevinskie[m] | _florent_: I’m adding altera unique chip ID and ADC support to litex. Would you like me to put them in dna.py and xadc.py or create new platform generic adc.py and chipid.py? | 17:12 |
| _florent_ | jevinskie[m]: nice, you can use generic names yes. Later we could convert adc.py to a directory and move more ADC in it. | 17:27 |
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| swetland | shorne_: absolutely. the C code is much more navigable | 18:50 |
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| Hammdist | I'm trying to generate the liteeth MAC for versa 5g in wishbone mode. https://paste.ee/p/1u6Cb. the generated module has only an output wire interrupt, not a complete wishbone attachment interface. did I miss an important step? | 20:04 |
| Hammdist | well I tried with exactly this config: https://raw.githubusercontent.com/antonblanchard/microwatt/master/liteeth/gen-src/arty.yml and I get the same results (no wishbone on the module). might be some kind of regression? | 20:10 |
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| Hammdist | 8733aecf89d56e1215dedd491bcd8fdea3fb21d9 is the first bad commit | 20:38 |
| Hammdist | well if I git revert that commit relative to master it seems to work | 20:47 |
| Hammdist | so where can I find a sample driver for the wishbone interface? | 21:20 |
| Hammdist | found something that might be helpful for me though I'm not proficient in rust at all: https://docs.tockos.org/src/litex/liteeth.rs.html | 22:08 |
| tpb | Title: liteeth.rs - source (at docs.tockos.org) | 22:08 |
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