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| swetland | maybe more of a vexriscv than litex question --- vexriscv appears to implement lr/sc but not amo*, which does not seem unreasonable, *but* it also seems to hang forever on amo* instructions which is annoying. any ideas if there's an easy fix for this? | 10:34 |
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| gatecat | swetland: the "linux" variant cores with a dcache should have amo* enabled too: https://github.com/litex-hub/pythondata-cpu-vexriscv/blob/cdfb2306087a680df65153760fd41002e316ad30/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala#L150 | 10:48 |
| gatecat | however, it should also be possible to set up an illegal instruction trap handler to emulate the amo's | 10:48 |
| gatecat | like in the old emulator code before these were done in hw for linux: https://github.com/smunaut/iCE40linux/blob/9a28d6a2b1f974d7caad24596fbbd82899f3f0f7/firmware/bios/main.c#L499-L534 | 10:49 |
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| swetland | hmmm. weird. I'll have to dig a bit deeper and figure out what I'm doing wrong | 21:20 |
| swetland | I wish vexriscv had a csr with a bitfield indicating which features were present so I could interrogate a generated core ^^ | 22:22 |
| swetland | okay.... updated my litex checkout to latest git versions and now running the target python script doesn't generate the build/$target/... stuff and compile the firmware | 22:28 |
| swetland | ah... it now wants --build... but now the design no longer fits in the icesugar-pro... uses a lot more DP16K than before I updated. not sure why | 22:39 |
| swetland | ah. misplaced my patch to reduce the video fifo depth | 22:41 |
| cr1901 | On one hand, the number of RV extensions is... bad. On the other, I think the base ISA is excellent minimalism for putting smol cores in smol places (no MUL/DIV). | 23:12 |
| cr1901 | So I'm torn :P | 23:12 |
| swetland | yeah RV32I is a nice baseline and even RV32IMA is pretty light to run a slightly larger system without a lot of cruft | 23:14 |
| cr1901 | weren't you doing a 16-bit RISC a long time ago? Would be curious if anything came of the hardware impl | 23:15 |
| cr1901 | all CPUs are friends :) | 23:15 |
| swetland | gatecat: found it: bugs with linker script and bss init code resulted in failure to zero some variables -- qemu memory appears to be zero on boot, but not so on the actual sdram | 23:16 |
| swetland | cr1901: I was! haven't had time to play with it for a while | 23:16 |
| cr1901 | Still would be curious to see it completed eventually, to add to the "me-too" RISC pile :) | 23:17 |
| swetland | at the moment I'm getting setup for some little workshops I'm doing on how-oses-work / how-to-write-an-os. using RV32IMA w/ U/S/M + MMU on Qemu and ECP5 (Litex/VexRISCV) as the platform | 23:17 |
| cr1901 | I like RV's base ISA a LOT, and... not much else. And I kinda buy the conspiracy theory that RV was designed to require insn fusion for high performance. And the insn fusion for RV was patented. | 23:18 |
| swetland | I had not heard that. interesting. I like it as a "real" modern ISA with solid gcc/clang support and readily available soft implementations. nice teaching tool. not deeply invested in it otherwise as yet | 23:20 |
| cr1901 | Well, don't take me too seriously re: the conspiracy theory. The patent part is true, the rest is just speculation b/c nothing would surprise me anymore :P | 23:21 |
| swetland | it's nice to get people up to speed and hands-on with something supported, documented, reasonably clean, and not yet burdened with a few decades of evolution (say vs x86/x64/arm/etc) | 23:21 |
| swetland | also I finally found a diagram making tool for linux that's not hateful: https://twitter.com/dnaltews/status/1525234050343915520 | 23:22 |
| tpw_rules | drawio? | 23:30 |
| swetland | yah | 23:33 |
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