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| zyp | _florent_, I'm having some issues with https://github.com/enjoy-digital/litex/commit/38a7b1fee0f7a412481e6085b94a5d1ab70cdc74 | 09:34 |
|---|---|---|
| zyp | it's making my build fail with ValueError: Multiple submodules with local clock domains cannot be anonymous | 09:34 |
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| AndrewD | tnt: thanks, I assumed there must be a reason for the pattern but using litex is my first reason to take python seriously. I've discovered I quite like it! | 09:50 |
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| _florent_ | zyp: ok, I'll see if I can do this differently | 13:08 |
| tnt | _florent_: btw, tried again with updated litex/litepci still same issue in x8 :/ | 13:18 |
| tnt | So I if you have the litescope code to probe the inside, I can try that next. | 13:19 |
| _florent_ | tnt: Thanks, you could use this: | 13:29 |
| _florent_ | https://www.irccloud.com/pastebin/VYoJsM8z/ | 13:29 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 13:29 |
| _florent_ | and trigger on m_axis_rc.valid before starting the dma_test | 13:30 |
| _florent_ | to see if you the DMA Reader receives the first completions. And once stuck, if you can do another capture to see if that's rc channel that is stuck (valid=1, ready=0) | 13:31 |
| tnt | Ack. | 13:33 |
| _florent_ | zyp: not very clean, but this should fix your build. I'll probably have another look at it. | 14:10 |
| _florent_ | https://github.com/enjoy-digital/litex/commit/c400479174847a3f107236badc156d9dbd8fd41e | 14:10 |
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| tnt | _florent_: https://i.imgur.com/GxPStW2.png and https://i.imgur.com/IZlV2Hm.png | 14:39 |
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| Melkhior | hello; what would be the 'recommended' way to clear (set all words to 0) a Memory() object? I find myself in need of clearing the tag memory of a wishbone cache to "flush" it but not sure how to do that (no lines need eviction as I converted it from write-back to write-through/write-no-allocate) | 15:24 |
| Melkhior | thanks | 15:24 |
| Melkhior | (I tried a ResetInserter() but those don't seem to work on Memory ?) | 15:26 |
| _florent_ | tnt: ok, thanks. So it seems to start correctly and nothing indicates that a channel is blocked when it's hanging. | 16:44 |
| _florent_ | tnt: it would be interesting to add these signals: | 16:44 |
| _florent_ | https://www.irccloud.com/pastebin/wDTzB9hD/ | 16:44 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 16:44 |
| _florent_ | Melkhior: A Block RAM does not have a reset pin, you'll have to implement your own logic to do clear the sections you want | 16:53 |
| _florent_ | Melkhior: You could share one of the port of the Memory for this, or add another specific. But if you already have 2 ports, adding another will prevent the use of BlockRAM. | 16:55 |
| Melkhior | @_florent_ OK thanks! it should only have one port (it's basically the tag_mem from the wishbone cache) so I could add a loop to reset all tag bits to zero | 16:58 |
| Melkhior | (or I could try and do some snooping to only invalidates lines that have been write-touched by the host... but that's probably harder) | 17:01 |
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