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| rowang077[m] | I have a question about SDR RAM phy interface in litesdram. | 15:41 |
|---|---|---|
| rowang077[m] | If I look at the data lines here: https://github.com/enjoy-digital/litedram/blob/master/litedram/phy/gensdrphy.py#L78 | 15:41 |
| rowang077[m] | They are outputted using a tristate buffer. | 15:41 |
| rowang077[m] | But shouldn't the signal going from the FPGA to the tristate buffer contain an `SDROutput` IO and the signal coming from the tristate buffer into the fpga contain an `SDRInput`? | 15:42 |
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| zyp | rowang077[m], I would assume a SDRTristate is a bundle of Tristate, SDRInput and SDROutput primitives | 17:46 |
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| rowang077[m] | zyp: I'll use ECP5 as an example because that's what I'm interestedn. See here https://github.com/enjoy-digital/litex/blob/master/litex/build/lattice/common.py#L153 it uses a `trellis_io` block. Which get's translated to a `BB*` primitive. If I look at Lattice library pdf here: https://www.latticesemi.com/-/media/LatticeSemi/Documents/Diamond312/Diamond_312_fpga_library.ashx?document_id=53106. Under the `BB` primitive it doesn't have any | 17:56 |
| rowang077[m] | input or output registers. | 17:56 |
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| tnt | _florent_: did you figure out the declink pcie+dram issue ? | 18:23 |
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| zyp | rowang077[m], you're looking at the Tristate implementation, not SDRTristate | 18:45 |
| zyp | here's the SDRTristate implementation: https://github.com/enjoy-digital/litex/blob/master/litex/build/io.py#L76 | 18:47 |
| zyp | in other words, when you instance a SDRTristate, it creates a Tristate, a SDRInput and a SDROutput instance, which in turn creates BB, IFS1P3BX and OFS1P3BX primitives, respectively | 18:51 |
| _florent_ | tnt: sorry I haven't searched yet for the decklink, but I started looking at an issue that seems similar to https://github.com/enjoy-digital/litepcie/issues/90 where LitePCIe is generated as a standalone core and integrated in more traditional design. We also saw the dma_test hanging (DMA Writer is working but DMA Reader not). I'll continue investigating on this and will keep you updated. | 19:31 |
| tnt | _florent_: mmm ... I'm trying to build the bitstream for the declink but I'm getting hold violations :/ | 19:33 |
| tnt | trabucayre: mmm, ever looked at the kintex ultrascale parts ? | 19:39 |
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