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| _florent_ | tnt: Thanks for the LiteScope PR. I'm currently debugging a design with LiteScope so will switch to it to do some initial tests with it. | 08:17 |
|---|---|---|
| tnt | _florent_: ack. Curious to see how it works out for you. Is that through UART or JTAG or Ethernet or ? | 08:29 |
| tnt | I guess most gain are for narrow deep captures. ( I was using < 96 signals but over 65k samples ) | 08:30 |
| tnt | _florent_: btw : https://github.com/smunaut/litex/commit/9024232222338e2ab3bd12b662ef625ba5904a97 | 08:47 |
| tnt | I mean, it's WIP, but it works ... just unusably slow. | 08:47 |
| _florent_ | tnt: I'm debugging over JTAGBone on this design. I did a first review of the code in the PR, it looks good, thanks! | 08:49 |
| _florent_ | tnt: I just also did a first capture with it, it seems to work (and faster than before) | 08:50 |
| _florent_ | tnt: for your ZynqMP/JTABone, you can do a PR if it's working. I'll review it and will also test it on 7-Series/ECP5. If working on other FPGAs, we could merge and we could then see how to improve speed. | 08:54 |
| tnt | _florent_: huh no, it's working on ZynqMP, pretty sure it breaks everything else :) | 08:58 |
| _florent_ | tnt: ok, I now see you still have different implementations | 09:03 |
| tnt | yeah, I kept them here just to easily switch. | 09:05 |
| tnt | The second one should work in all cases (with openocd changes), but I suspect will slow things quite a bit when used with openocd. | 09:06 |
| tnt | The third one with 'bypass' set to 0 should work on non-zynqmp stuff, but it's not tested. | 09:06 |
| _florent_ | ok, I could help do some test on other boards if this can be useful | 09:09 |
| tnt | (err, I meant 'offset' not 'bypass' above). | 09:10 |
| tnt | You can try that commit on any other board, just setting offset=0 and check if it still works and if it's the same speed as before (in case I screwed up something that affects efficiency but not correctness). | 09:10 |
| tnt | I'll say that speed with the litescope improvements doing long bursts is much more tolerable than before. It's about 4x slower than UART but that's much better than 20x slower. | 09:11 |
| _florent_ | ok, I'll do some tests when I'll be done with other things (maybe this afternoon or tomorrow) | 09:14 |
| _florent_ | LiteScope over JTAGBone indeed seems much faster from the captures I'm currently doing | 09:15 |
| cr1901 | _florent_: Btw, your explanation on source-to-source makes sense now, thanks. Sorry for delay. Very distracted | 14:36 |
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| tnt | Bit of a migen question. I'm trying to do a platform.add_false_path_constraints(sys_ck, ...). But I don't have the 'sys_clk' signal handy there in the code. | 18:50 |
| tnt | I tried passing ClockSignal('sys') directly, but that doesn't work. | 18:50 |
| tnt | The only way I found so far is to create a new signal. Use comb += new_sig.eq(ClockSignal('sys')) and then use new_sig in the add_false_path_constraint. | 18:51 |
| tnt | Am I missing something or a more convenient way to do that ? | 18:51 |
| _florent_ | tnt: not sure there is a more convenient way, but I could have a look tomorrow | 18:57 |
| _florent_ | tnt: I've been using LiteScope quite a bit today and haven't had issue with the new code | 18:59 |
| tnt | _florent_: Great, good to hear it's working good :) | 19:00 |
| tnt | Only thing I forgot to test is if Constant(0,0) (i.e. zero width signal constant) is valid / accepted in migen. (would happen is the # of monitored signals is an exact multiple of 32). | 19:01 |
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