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| tnt | How does one write an async reset register in migen ? | 11:54 |
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| acathla_ | tnt, there is a AsyncResetSynchronizer in migen, not sure if that's what you're looking for but can be inspiring : https://github.com/m-labs/migen/blob/master/migen/genlib/resetsync.py | 12:32 |
| tnt | I saw that but there is literally nothing in there ... | 12:35 |
| acathla_ | tnt, it's handled by migen because you add it as a "special", and it seems to be platform dependant | 12:40 |
| tnt | yeah, but that doesn't help me then :) | 12:43 |
| tnt | I basically want like a Signal(8) but with a async reset rather than sync. | 12:43 |
| acathla_ | https://m-labs.hk/migen/manual/reference.html?highlight=signal#migen.fhdl.structure.Signal Doc of Signal, not sure it will help much. | 12:50 |
| tpb | Title: API reference — Migen 0.8.dev0 documentation (at m-labs.hk) | 12:50 |
| _florent_ | tnt: Reset is synchronous with Migen, to write an async reset, you have to do it in Verilog and an instance or use a Xilinx primitive directly | 13:43 |
| tnt | _florent_: tx for confirming what I suspected. | 14:43 |
| zyp | can't you just make a small clock domain for interacting with the particular signal and use an AsyncResetSynchronizer to drive the reset of the domain? | 15:03 |
| tnt | The goal of the reset async in this case would be to ensure reset works (i.e. output signal goes to defined state) when the clokc isn't running. | 15:04 |
| cr1901 | This is one of the things amaranth fixes, which has async_reset=True param for Signals | 15:21 |
| cr1901 | And indeed, helpful for resets w/o a clock (where only async resets work) | 15:21 |
| cr1901 | tnt: Btw, have any idea where this example went? https://github.com/smunaut/ice40-playground/blob/icepick/projects/icepick_test/rtl/sense.v | 15:24 |
| tnt | cr1901: mmm, I probably just removed the branch from the public tree since it was for hardware that nobody has. | 15:29 |
| cr1901 | Ahhh, I'm just studying this: https://github.com/gregdavill/OrangeCrab-test-sw/blob/main/hw/rtl/analog.py | 15:29 |
| cr1901 | Which said it was adapted from your code | 15:30 |
| tnt | cr1901: https://gist.github.com/smunaut/bb87ed1ccbf6389977ab2be65f427625 | 15:31 |
| tnt | Yeah, the orange crab analog part is a copy of what I did on the icepick. | 15:32 |
| cr1901 | tnt: Thanks, I've been on a bit of an ADC kick lately... hope it ends soon, b/c reading about them for too long makes my head hurt :D | 15:43 |
| tnt | lol. I'm not claiming that ADC method is any good btw, but it worked good enough for me. You could also do sigma-delta with the same external hw but I didn't want a high frequency toggling node. A 'single conversion' kind of thing was more what I needed. | 15:46 |
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| cr1901 | I wanted an interrupt that automatically lets you know when a measurement is done, but that's like 5 lines of code for a LiteX core | 15:56 |
| cr1901 | Otherwise, single conversion is fine | 15:56 |
| tnt | _florent_: So I'm faced with the classic "vivado analyzes path it shouldn't" between pcie domain and sys_clk domain. | 15:59 |
| tnt | If I do : platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) it doesn't help. | 15:59 |
| tnt | If I do : platform.toolchain.pre_placement_commands.append("set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets pcie_clk]] -asynchronous") | 16:00 |
| tnt | then that last one works. The resulting .xdc is the same but the second also has that line in the `.tcl` | 16:00 |
| _florent_ | tnt: it could be related to the fact that synthesis of the PCIe PHY/LiteX design are done separately and previous constraint is ignored by Vivado. It's indeed sometimes painful to have false paths applied correctly | 16:04 |
| _florent_ | tnt: that's also some cases where LiteX does not necessarily simplify things with the extra-layers | 16:05 |
| tnt | mmm. But the IP are done both before the read_xdc and before the "# Add pre-placement commands" where that also ends up. | 16:10 |
| tnt | I guess the [get_clock / get_net ...] might not work because that done before synthesis so those don't exist yet ? | 16:12 |
| cr1901 | tnt: (Last q, I promise) What's the point of this line incrementing sense_val by 2? https://gist.github.com/smunaut/bb87ed1ccbf6389977ab2be65f427625#file-sense-v-L152 | 16:19 |
| cr1901 | err sense_cnt by 2*. It's an edge detector (pos/neg edge of inpt clock), but I don't see why you need to incr by 2 once you've reached the comparator transistion | 16:19 |
| tnt | it increments by 1 or 2 depending on which bits are sampled at 1. | 16:22 |
| tnt | The thing (at least in the ice40), at the transition point, it tends to sometime sample a 1, sometimes a 0 and you get a more precise result by counting all the 0 (or all the 1) over a fixed interval rather than measuring the cycles it takes to get to the first one or first zero. | 16:24 |
| cr1901 | Oh wait... concat in Verilog is {bit1, bit0} if your signal is declared [1:0] isn't it? | 16:25 |
| cr1901 | Okay, this makes sense, I mixed up the concatenation order | 16:28 |
| cr1901 | Effectively, you're using both of input_clk's edges to the SB_IO to double the resolution/number of measurements taken | 16:34 |
| tnt | cr1901: precisely. | 18:03 |
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