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| mikek_Xtrx | Hello All: I have received some critical warnings when compiling the fairwaves_xtrx project. Should I be concerned about this? | 02:42 |
|---|---|---|
| mikek_Xtrx | WARNING: [Vivado 12-3523] Attempt to change 'Component_Name' from 'pcie_s7' to 'pcie' is not allowed and is ignored. | 02:42 |
| mikek_Xtrx | WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'Legacy_Interrupt' from 'NONE' to 'None' has been ignored for IP 'pcie_s7' | 02:42 |
| mikek_Xtrx | # synth_ip $obj | 02:43 |
| mikek_Xtrx | CRITICAL WARNING: [Vivado 12-5447] synth_ip is not supported in project mode, please use non-project mode. | 02:43 |
| mikek_Xtrx | Resolution: Verify the create_clock command was called to create the clock object before it is referenced. | 02:43 |
| mikek_Xtrx | INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Nov2021/xtrx_julia/build/fairwaves_xtrx_platform/gateware/fairwaves_xtrx_platform.xdc:361] | 02:43 |
| mikek_Xtrx | CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks -of_objects [get_nets rfic_clk]]'. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Nov2021/xtrx_julia/build/fairwaves_xtrx_platform/gateware/fairwaves_xtrx_platform.xdc:361] | 02:43 |
| mikek_Xtrx | Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. | 02:43 |
| mikek_Xtrx | CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group '. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Nov2021/xtrx_julia/build/fairwaves_xtrx_platform/gateware/fairwaves_xtrx_platform.xdc:361] | 02:43 |
| mikek_Xtrx | Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. | 02:43 |
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| mikek_Xtrx | CRITICAL WARNING: [Constraints 18-4427] You are overriding a physical property set by a constraint that originated in a read only source. Your changes will not be saved with a project save. If you wish to make this change permanent, it is recommended you use an unmanaged Tcl file. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Nov2021/xtrx_julia/build/fairwaves_xtrx_platform/gateware/fairwaves_xtrx_platform.gen/sources_1/ip/pcie_s7/source/pcie_s7-P | 02:44 |
| mikek_Xtrx | CIE_X0Y0.xdc:117] | 02:44 |
| mikek_Xtrx | CRITICAL WARNING: [Constraints 18-4427] You are overriding a physical property set by a constraint that originated in a read only source. Your changes will not be saved with a project save. If you wish to make this change permanent, it is recommended you use an unmanaged Tcl file. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Nov2021/xtrx_julia/build/fairwaves_xtrx_platform/gateware/fairwaves_xtrx_platform.gen/sources_1/ip/pcie_s7/source/pcie_s7-P | 02:44 |
| mikek_Xtrx | CIE_X0Y0.xdc:118] | 02:44 |
| mikek_Xtrx | I have the "home" version of the vivado software, Do I need to have an upgraded version for clock support? | 02:44 |
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| mikek_Xtrx | Again, I am not very familar with vivado software.. thanks! MikeK | 02:46 |
| mikek_Xtrx | the build was successful, and created a Bin file. I just want to make sure it's ok before I program the XTRX device. Thanks. | 02:47 |
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| mikek_Xtrx | yeah got it to work! Counting LEDS on DECA board! :) | 14:30 |
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| Thanos634 | Hi Litex team, I am trying to create a SoC to test through the openroad toolchain (https://openroad.readthedocs.io/en/latest/user/GettingStarted.html) | 19:16 |
| Thanos634 | Do you recommend using litex for asic? Do you have any suggestions/pointers to any related documentation or efforts of other users? | 19:16 |
| Finde | afaik this is being done by efabless for caravel, not sure if this is the right repo but it's what I got from a quick google: https://github.com/efabless/caravel_mgmt_soc_litex | 19:24 |
| _florent_ | Hi Thanos634, the best would be to create specific build backend for each specific ASIC flow. I'm also building a generator to ease LiteX SoC generation and use in designs (without using the LiteX build system). This could also be useful for ASIC flow. | 19:37 |
| Thanos634 | Thanks a lot Finde I Am looking into it! | 19:41 |
| _florent_ | eFabless indeed seems to use LiteX for Caravel, but I'm not sure I would have done it this way. I'm not sure for example they are using litex_sim or prototyping on hardware through boards available litex_boards. | 19:41 |
| Thanos634 | _florent_ I am not sure what you mean. My initial plan is to create the verilog model and then go thought the available open source tools to end up with a gds. | 19:43 |
| _florent_ | Thanos634: The aim of the LiteX SoC generator is to simplify SoC generation (so what you call verilog model) | 19:45 |
| _florent_ | Thanos634: For now, you can also generate a simple SoC with: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/simple.py | 19:46 |
| _florent_ | and use one of the existing build backend to specialize the code | 19:47 |
| Thanos634 | Exaclty. This is why i think it is a good idea to use litex. But as far as I can see it is targeting fpga tho. I just thought to ask in the channel if that should deter me. | 19:47 |
| Thanos634 | It looks like it should not :) | 19:47 |
| _florent_ | python3 -m litex_boards.targets.simple litex_boards.platforms.digilent_arty --no-compile-software | 19:49 |
| _florent_ | python3 -m litex_boards.targets.simple litex_boards.platforms.terasic_de0nano --no-compile-software | 19:49 |
| _florent_ | Here it will generate a simple SoC specialized for Xilinx or Altera/Intel | 19:51 |
| _florent_ | You can then replace the few FPGA primitives in the code and test with OpenLane | 19:51 |
| _florent_ | or create the OpenLane build backend that will allow direct specialization of the code | 19:52 |
| Thanos634 | Hm, I see. I like the second idea a lot! Thanks | 19:52 |
| _florent_ | I've been using LiteX on small parts of ASIC in the past (and also for verification), but this is not open-source | 19:53 |
| _florent_ | it would be nice in the future to support the open-source flows | 19:53 |
| Thanos634 | Of course. I am working on this with a friend for his thesis. If it goes well we will provide documentation for sure! | 19:59 |
| _florent_ | Thanos634: great, happy to provide specific help if needed | 20:05 |
| Thanos634 | Thanks a lot _florent_ ! | 20:30 |
| Thanos634 | I will keep you posted | 20:30 |
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