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cr1901 | Well, LiteX is more about putting cores together and providing an integrated environment for SoCs... the HDL used in principle shouldn't matter (as long as all the components can be connected) | 00:44 |
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cr1901 | Anyways, LiteX will still be incredibly useful even if it moves away from Migen | 00:44 |
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_florent_ | cr1901: The idea is still to allow Migen use (as it is possible with VHDL/Verilog, etc...), the limitations with Migen are not really technical (since can be worked around without too much difficulties and in LiteX (& cores) 75% of code is probably Python / 25% logic description through Migen) but having the control on the HDL generation can offer more flexibility, so that's why I'm exploring this. | 07:27 |
_florent_ | cr1901: There are also some regular critisims about the fact that LiteX still uses Migen vs nMigen/Amaranth and I'm a bit bored about this so just want to explore a solution that will be the more convenient for my projects and allow me have full control of the HDL generation. | 07:31 |
_florent_ | shorne: the kind of regression that is not easy to track... :( I hope it won't take too long to figure out. Do you think we should use a fixed sha1 for mor1kx in litex_setup until you figure it out? (https://github.com/enjoy-digital/litex/blob/master/litex_setup.py#L97) | 07:41 |
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cr1901 | _florent_: Well, I'll just have to wait and see what you have in mind. I think a better question I want to ask is: How will the process of creating a new/out-of-tree LiteX design change with your new plan? | 16:47 |
cr1901 | With the process of building the in-tree examples change at all, or will that process be user-invisible (i.e. the arguments to build a litex-board SoC won't change?)? | 16:48 |
_florent_ | cr1901: The idea is to make it transparent to users (otherwise this should probably be a different project than LiteX) and I'm not expecting to change the SoC parameters (and if so for some also provide a compatiblity layer). | 18:10 |
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jevinskie[m] | By traceability do you mean something like source to source debug maps? That would be fantastic | 21:36 |
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