Saturday, 2022-02-05

*** tpb <[email protected]> has joined #litex00:00
cr1901Well, LiteX is more about putting cores together and providing an integrated environment for SoCs... the HDL used in principle shouldn't matter (as long as all the components can be connected)00:44
cr1901Anyways, LiteX will still be incredibly useful even if it moves away from Migen00:44
*** Emantor_ <[email protected]> has quit IRC (Quit: ZNC - http://znc.in)02:20
*** Emantor <[email protected]> has joined #litex02:20
*** bl0x_ <bl0x_!~bastii@p200300d7a718af00d3bcd8a9c87bbda8.dip0.t-ipconnect.de> has quit IRC (Ping timeout: 250 seconds)02:52
*** bl0x_ <bl0x_!~bastii@p200300d7a7384c00c372d7e9b99ad207.dip0.t-ipconnect.de> has joined #litex02:54
*** Melkhior_ <Melkhior_!~Melkhior@2a01:e0a:1b7:12a0:225:90ff:fefb:e717> has joined #litex03:19
*** Melkhior <Melkhior!~Melkhior@2a01:e0a:1b7:12a0:225:90ff:fefb:e717> has quit IRC (Ping timeout: 240 seconds)03:21
*** Degi_ <[email protected]> has joined #litex04:02
*** Degi <[email protected]> has quit IRC (Ping timeout: 256 seconds)04:03
*** Degi_ is now known as Degi04:03
*** Martoni <Martoni!~Martoni@2a03:d604:103:600:2ad2:44ff:fe23:2f72> has joined #litex06:50
_florent_cr1901: The idea is still to allow Migen use (as it is possible with VHDL/Verilog, etc...), the limitations with Migen are not really technical (since can be worked around without too much difficulties and in LiteX (& cores) 75% of code is probably Python / 25% logic description through Migen) but having the control on the HDL generation can offer more flexibility, so that's why I'm exploring this.07:27
_florent_cr1901: There are also some regular critisims about the fact that LiteX still uses Migen vs nMigen/Amaranth and I'm a bit bored about this so just want to explore a solution that will be the more convenient for my projects and allow me have full control of the HDL generation.07:31
_florent_shorne: the kind of regression that is not easy to track... :(  I hope it won't take too long to figure out. Do you think we should use a fixed sha1 for mor1kx in litex_setup until you figure it out? (https://github.com/enjoy-digital/litex/blob/master/litex_setup.py#L97)07:41
*** Martoni <Martoni!~Martoni@2a03:d604:103:600:2ad2:44ff:fe23:2f72> has quit IRC (Ping timeout: 256 seconds)08:18
*** Martoni <Martoni!~Martoni@2a03:d604:103:600:2ad2:44ff:fe23:2f72> has joined #litex08:58
*** Martoni <Martoni!~Martoni@2a03:d604:103:600:2ad2:44ff:fe23:2f72> has quit IRC (Ping timeout: 250 seconds)09:04
*** Martoni <Martoni!~Martoni@2a03:d604:103:600:2ad2:44ff:fe23:2f72> has joined #litex10:09
*** Martoni <Martoni!~Martoni@2a03:d604:103:600:2ad2:44ff:fe23:2f72> has quit IRC (Ping timeout: 252 seconds)12:06
cr1901_florent_: Well, I'll just have to wait and see what you have in mind. I think a better question I want to ask is: How will the process of creating a new/out-of-tree LiteX design change with your new plan?16:47
cr1901With the process of building the in-tree examples change at all, or will that process be user-invisible (i.e. the arguments to build a litex-board SoC won't change?)?16:48
_florent_cr1901: The idea is to make it transparent to users (otherwise this should probably be a different project than LiteX) and I'm not expecting to change the SoC parameters (and if so for some also provide a compatiblity layer).18:10
*** Martoni <Martoni!~Martoni@2a03:d604:103:600:2ad2:44ff:fe23:2f72> has joined #litex18:50
*** Martoni <Martoni!~Martoni@2a03:d604:103:600:2ad2:44ff:fe23:2f72> has quit IRC (Ping timeout: 252 seconds)20:20
jevinskie[m]By traceability do you mean something like source to source debug maps? That would be fantastic21:36
*** ewen <[email protected]> has joined #litex22:30

Generated by irclog2html.py 2.17.2 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!