Saturday, 2022-01-22

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MoeIcenowyoops GW1NR-9C QN88P PSRAM has two chips18:35
MoeIcenowyand their port definition just doubles the width of one port18:36
MoeIcenowy(the PSRAM is in fact HyperRAM too and can be driven with litehyperbus18:36
MoeIcenowyweird, what should I do...18:36
MoeIcenowywell a top design port can only be requested once, but I can then slice it...19:21
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_florent_MoeIcenowy: I started the HyperRAM port on the 4K, it was compiling correctly but not working yet, I haven't investigated yet20:38
_florent_this should be a bit similar on the 9K20:38
_florent_https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/sipeed_tang_nano_4k.py#L54-L6020:38
_florent_https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/sipeed_tang_nano_4k.py#L105-L11920:39
_florent_here is a blog post where they got it working: https://justanotherelectronicsblog.com/?p=98620:42
tpbTitle: Sipeed Tang 4K ramblings - jaeblog jaeblog (at justanotherelectronicsblog.com)20:42
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