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| yootis | _florent_: just a heads up, but building docs won't work on systems with Python 10 (like Fedora 35). The problem is in either sphinxcontrib-wavedrom or wavedrom. Some python imports moved around and/or they are using a deprecated feature that finally went away. | 00:52 |
|---|---|---|
| tpw_rules | do you mean 3.10? | 00:53 |
| yootis | sorry, python 3.10 | 00:54 |
| yootis | Python 10 would be awesome, though :) | 00:54 |
| yootis | Maybe by Python 10 they'll get rid of the GIL... | 00:55 |
| tpw_rules | :D | 00:56 |
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| sajattack[m] | I don't want 7 more breaking releases of python | 01:19 |
| sajattack[m] | the way they handled the 2-to-3 transition was horrid | 01:19 |
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| _florent_ | yootis: I'll have a look on Monday, we did various small changes on the software at the end of the year for the XTRX/LMS7002M project | 11:36 |
| _florent_ | yootis: can you do a test with litepcie software before this: https://github.com/enjoy-digital/litepcie/commit/0c0c3b72241139e0b2e5e61288267d9732f7e5f0 | 12:00 |
| _florent_ | yootis: I'm going to build a machine for CI hardware tests to catch this more easily in the next months with several boards integrated (PCIe ones: ex Acorn, BCU1525, etc...) or connected (ex: Arty, Butterstick, Fomu, etc...). | 12:04 |
| mntmn | _florent_: i've set up my litex framebuffer to eDP pipeline with 2 external bridge chips in linux-on-litex-vexriscv, but i've run into a problem. drm crashes with "Unable to handle kernel access to user memory without uaccess routines". do i have to turn this on somewhere? | 12:17 |
| mntmn | i see that uaccess.S exists in arch/riscv/lib, but not sure if that's not enabled or something | 12:19 |
| mntmn | hmm, looks like this is included if CONFIG_MMU=y, which is def. y | 12:21 |
| mntmn | i don't get it. | 12:21 |
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| mntmn | hmm, maybe i'm running into this https://www.codethink.co.uk/articles/2021/RISC-V-user-space-access-oops/ | 12:25 |
| tpb | Title: RISC-V User space access Oops (at www.codethink.co.uk) | 12:25 |
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| mntmn | ah, probably this is just a bad pointer and misleading error message? | 12:48 |
| mntmn | yep, sorry | 13:13 |
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| nickoe | I wonder what this reall means ... "ValueError: ('Could not lower all specials', {<migen.fhdl.specials.Instance object at 0x7f8ac2fb6e00>})" Trying to use platform.add_source to add a verilog module, then the Instance of it and then add that instance to self.specials... | 21:49 |
| nickoe | sajattack[m]: Wasn't it more about library maintainers not prioritizing making their module compatible with both in the transition period that sorta "killed it"? | 21:51 |
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| nickoe | I am trying to simulate part of my design with SimPlatform without a COU, ask without SocCore. So maybe I need that somehow? | 21:55 |
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| sajattack[m] | <nickoe> "sajattack: Wasn't it more..." <- It was about making a hard split in the language and not maintaining backwards compatibility. Whether maintainers responded well to having to make changes is irrelevant. The lang maintainers should have provided a smoother transition, like Rust does with "editions" | 22:31 |
| sajattack[m] | https://doc.rust-lang.org/edition-guide/editions/index.html | 22:32 |
| tpb | Title: What are editions? - The Edition Guide (at doc.rust-lang.org) | 22:32 |
| sajattack[m] | * It was about making a hard split in the language and not maintaining backwards compatibility. Whether library maintainers responded well to having to make changes is irrelevant. The lang maintainers should have provided a smoother transition, like Rust does with "editions" | 22:32 |
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| nickoe | ok | 22:46 |
| nickoe | Can't one use a migen test bench with a litex soc? | 22:46 |
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| nickoe | I don't get why I get termios.error: (25, 'Inappropriate ioctl for device') with the SoCMini | 22:48 |
| nickoe | as my BenchSoC | 22:48 |
| nickoe | Mm, I cam not sure I understand how I can make a CPU-less simulation with the MiniSoC and make a testbench for some modules in it. | 23:21 |
| nickoe | *SoCMini that is. | 23:21 |
| nickoe | mm, I see that run_simulation is used in test_adaptaion in litedram.. | 23:29 |
| nickoe | is it possible to make a test bench which can run use Instance of some verilog module with litex? It appears to me I can only run a "normal" simulation and not write a migen test bench and use run_simulation to use the testbench | 23:39 |
| nickoe | on it | 23:39 |
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