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| _florent_ | nickoe: --integrated-main-ram-size parameter allows you to add a Main Ram to your SoC when your board does not have SDRAM. This will be implemented in block rams and size will of course be limited compared to a propoer SDRAM, but this is useful when for test or to embed a small firmware in your SoC in addition to the BIOS. | 06:48 |
|---|---|---|
| _florent_ | That's what is done currently for the XTRX development, the SoC has the BIOS + Firmware to initialize/test the XRTX. In the end we'll probably just have this firmware but keeping the BIOS for now is useful to be able to update/reload the firmware with litex_term. | 06:48 |
| _florent_ | mikek_DE1SOC: Can you identify your XTRX version? For now I'm focusing on the R4 for the develomment, but it should be possible (and not too complicated) to support the different revisions (ideally with the same bitstream not too much difference between revisions). | 06:51 |
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| nickoe | _florent_: I my case the RAM chip is on the SoM board, but outside the FPGA - so is that still "integrated main ram"? | 10:24 |
| nickoe | https://www.enclustra.com/en/products/fpga-modules/mars-ax3/ | 10:25 |
| tpb | Title: Enclustra FPGA Solutions | Mars AX3 | Xilinx Artix-7 28nm FPGA Module | 7A35T | 7A50T | 7A100T (at www.enclustra.com) | 10:25 |
| _florent_ | nickoe: Sorry, I'm trying to answer the questions but think you can answer this one :) | 10:30 |
| nickoe | It is a terminology question, where I am trying to undenrstand if it is still considered "main integrated ram" when it is on the PCB, but not in the FPGA chip. I would guess not, but the reason to understand this is if I should still keep muching around with that option or not. | 10:32 |
| nickoe | My main problem is that self.sdram is not avaiable when I use that. | 10:32 |
| _florent_ | integrated_main_ram is useful to have a small RAM implemented in Block Ram when your FPGA does not have external memory | 10:39 |
| _florent_ | Since you have a DDR3 on your board, you don't necessarily need it. And if you did the board support similar to the others boards, DDR3/integrated-main-ram will be mutually exclusive | 10:40 |
| _florent_ | One difference between integrated-main-ram and external SDRAM is that the external SDRAM canno't be initialized (except in simulation, but will not be possible on hardware) | 10:41 |
| nickoe | Ok cool, that makes more sense. So in my case where I did mange to make the mem test pass but not running that levelign thing you suggested, it should be good for me to use the real "external" sdram. | 10:45 |
| nickoe | But I also still wonder why the memcheck really faliled in the way it did, becuase this worked in april or there about. It is just a bit hard to test with the old code as I asume there are too may repos that I need to checkout to and arbitrary older date. | 10:46 |
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| nickoe | I am not sure how to interpret those "graphs" from the sdram_init in the bios | 10:51 |
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| _florent_ | nickoe: write latency calibration was added for some Ultrascale(+) config, it has been working correctly with the other 7-Series board but seems to cause issue on your board. | 12:23 |
| _florent_ | nickoe: for now you can disable it and we'll try to fix later (I'm not able to spend time on this now and don't have a hardware to reproduce currently) | 12:23 |
| _florent_ | nickoe: if you want to contribute the mars_ax3 support to litex_boards, feel also free to create an issue for this | 12:24 |
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| nickoe | I can certainly add it, but I don't know who else uses it | 13:48 |
| tnt | _florent_: the CS version should all be rev4 but 35T. | 14:17 |
| tnt | I'm probably like one of 5 people or so (outside fairwaves) with a rev3. | 14:18 |
| tnt | (Unrelated but ... I've been cleaning all my jesd code and tests .... and of course I broke everything ... damnit) | 14:19 |
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| SpaceCoaster | Anyone have an example for building the zynq+arm soc? | 15:39 |
| nickoe | tnt: Just curius, what are you working on? | 16:13 |
| nickoe | *curious that is | 16:16 |
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| mikek_DE1SOC | florent: OK will check tonight! I did mange to get the images compiled and working for the kernel driver magically. But still need to understand the process of the BIOS + Firmware for the XTRX.. This is ALL new to me! But looks REALLY Fun! | 16:31 |
| mikek_DE1SOC | But I am still not going to burn to talk to the card yet until I really understand what;s going on... I am still new to the X86 host thing too... ANY Document ion where you can point me towards! Would be great. | 16:32 |
| mikek_DE1SOC | I did see the quick notes in the fairwaves.py file... But if ther eany errors I would need a better understanding of what's going on.. I really want to keep the FPGA Chip in my board happy. | 16:33 |
| mikek_DE1SOC | tnt: I might be one of those other 5 guys! :) | 16:33 |
| mikek_DE1SOC | florent: BTW, that Overview graphic that you had on your Twitter feed for the XTRX/litex setup, where can I find that??? | 16:37 |
| nickoe | _florent_: Shouldn't something like this work just fine? "litex_sim --with-sdram --sdram-init demo.bin --sdram-module MT48LC16M16" It does not appaers to work for me when simulating. | 16:40 |
| nickoe | When it starts simulating the SoC it does show SDRAM: 65536KiB 32-bit @ 1MT/s (CL-2 CWL-2) , but it does not run the demo app, I just see the liftoff message. | 16:41 |
| nickoe | I am trying to _not_ use the integrated main ram | 16:41 |
| nickoe | But just the sdram | 16:41 |
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| nickoe | Huh!? When I build the bare metal demo against the build/sim it builds fine, but when I build it against my own target, it fails to link :S Why is this? I must be missing something, https://dpaste.com/BS4TYWKWQ.txt | 17:29 |
| mikek_DE1SOC | OOPS Sorry that came out wrong... :) just ignore this "But I am still not going to burn to talk to the card yet.... " :) | 17:32 |
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| nickoe | ah, ok, it was becasue my simulation model was outputting to the build/sim dir and not build/_myproject_ | 17:47 |
| nickoe | .....aaaandd then the demo.bin works on my board.. | 17:48 |
| nickoe | in simulation | 17:53 |
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| nickoe | mm, but it does not work on the target, hmm, even thought he memtests do appear to work fine | 18:33 |
| nickoe | loading with lxterm via uart | 18:33 |
| mikek_DE1SOC | nickoe: are you having issues loading the bin files with over the uart? | 18:36 |
| mikek_DE1SOC | For me, with the DE1-Soc, I find you have to lower the bitrate.. | 18:36 |
| mikek_DE1SOC | At one point i was able to use 3Mibs now sometimes i have to lower to 350k/s | 18:37 |
| mikek_DE1SOC | But i was using a Chinese RS232 to uart/jtag - USB converter. Since it's serial, maybe I was using the unit in a High EMI environment.. something to consider. | 18:39 |
| nickoe | It appers to transfer it correctly, the CRC check passes | 18:51 |
| nickoe | Like this https://dpaste.com/33YQ2FYZ5.txt | 18:52 |
| mikek_DE1SOC | ok great! :) | 19:02 |
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| nickoe | mikek_DE1SOC: But it does not run after that though. | 19:12 |
| nickoe | It works in the simulation | 19:12 |
| nickoe | But maybe it is becase my simulation is diffrent somehow, I mean the build made against the litex_sim script didn't boot in my projects sim | 19:13 |
| nickoe | maybe I should try to figure out what is different there. | 19:13 |
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