Thursday, 2021-12-02

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tcaltnt: to follow up, I dug out another iCEBreaker board, uploaded the same bitstream, and it worked 100% including tty.   So I think the board I was using could have degraded somehow (admittedly, I'm pretty casual about leaving boards lying about my desk among the clutter)00:05
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tnttcal: are both board the same revision ?07:07
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tcalyep -- v1.0e.    The old one *used* to work as expected, so whatever the flaw is, it snuck in in the last couple of months.07:15
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tnttcal: you can try iceprog -Q  in case some bitstream set the QE=0 non-volatile bit ...12:58
tntOn another subject: How does one deal with conflict in the CSR namespace :/  I have a custom i2c module with CSR and that prevents /libbase/i2c.c to build because the CSR_I2C_* values are the ones from my block and not the one from the default block (which I don't use).12:59
_florent_tnt: The BIOS is detecting presence of peripherals from presence CSR names , so for now I would recommend renaming your submodules13:11
tntack13:14
mntmnif i have some IP that has an interrupt line which is "level triggered", do i have to do some special stuff to make it work correctly with vexriscv interrupt lines?14:18
mntmni suspect that the cpu is triggering on edges only?14:19
mntmnto explain better, i can see in /proc/interrupts that the interrupt was recognized many times but it has stopped counting now:14:22
mntmn  4:       2673  SiFive PLIC  16 Edge      ue11-hcd:usb114:22
mntmnbut in litescope i can see that the interrupt line is high14:22
mntmn_florent_: any idea? does an interrupt line from hdl to vexriscv have to be pulsed?15:13
_florent_The cores from LiteX generate level triggered IRQs and that's what I also think is expecting VexRiscv-SMP PLIC implementation15:16
_florent_So your integration should be similar to IRQs generated from the UART/LiteEth cores15:16
mntmnhmm, but what could cause interrupts to not be registered?15:18
mntmni.e. i can see in litescope the line is high, but counter in /proc/interrupts does not increase15:18
_florent_I also don't explain it, unless we have a current missmatch between LiteX IRQs and expexted VexRiscv-SMP IRQs15:19
_florent_can you try to modulate the IRQ from your core, just to see if you then see the interrupt increasing?:15:20
_florent_https://www.irccloud.com/pastebin/83k2emuf/15:20
tpbTitle: Snippet | IRCCloud (at www.irccloud.com)15:20
mntmn_florent_: ok, i'm gonna try that15:22
mntmnthanks!15:24
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jersey99_florent_ Sorry for the bother, but I kind of want to see this through :) .. but are there any unassumed constraints about the BOOT_ROM_ADDRESS? The region seems to get allocated fine during build (base at 0x2000_0000), and I see the CPU trying to jump to that region after bios.15:51
jersey99And unexpectedly, setting the edianness to correct "little" didn't change the behavior15:52
_florent_before compiling the litex_bare_metal_demo, are you also updating:15:54
_florent_https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/demo/linker.ld#L2115:54
_florent_https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/demo/linker.ld#L3115:54
_florent_to use the new memory you added?15:54
mntmnhmm, what would make litescope not continue anymore after [running]...? (with immediate capture). i think i broke it by adding a 12-bit signal to the capture list15:56
mntmnah, the problem was outdated csr.csv16:15
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jersey99Oh .. Do I need to explicitly add the extra regions to the CPU? In that case, to my eyes, I don't see csr region being explicitly added. I will look into this17:59
tcaltnt: my iceprog doesn't seem to have "-Q" ?18:00
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jersey99_florent_ .. Thanks a lot for your help. This makes a lot of sense, and works :)19:39
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jersey99_florent_ I made a minor edit here ( https://github.com/enjoy-digital/litex/wiki/Load-Application-Code-To-CPU ) in regards to my experience. Maybe you could say something about the linker script (I understand it's a side detail).21:46
tnttcal: oh, my bad, this PR never got merged ... https://github.com/YosysHQ/icestorm/pull/28322:09
bjonnhthose digilent boards are shipping from Taiwan!22:12
tcaltnt: thanks for the pointer, hopefully I can check tonight if it unjams the board 22:40
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