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| cr1901 | _florent_: This may be a silly q, but... why is the "\n" on this line in a raw string? https://github.com/enjoy-digital/litex/blob/9ecb1e61a9cb77167db3cb3d709d2bff4193235d/litex/gen/fhdl/verilog.py#L50 | 02:00 |
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| _florent_ | cr1901: | 08:07 |
| _florent_ | cr1901: I should change it, I was not happy with it. I'll do another pass on verilog.py soon. | 08:08 |
| _florent_ | DerekKozel[m]: Sean Blakley was here a few days ago (smb784) | 08:09 |
| _florent_ | sajattack[m]: I used the Crossover UART very recently while adding the Fairwaves XTRX and the crossover UART hasn't evolved recently, so not sure to understand your issue. | 08:12 |
| _florent_ | sajattack[m]: But as discussed, I'll try to improve the serialboot upload speed over PCIe soon, so will also do a test on this | 08:13 |
| sajattack[m] | ok yeah, I don't have a lot to go off of either, but I built rocket linux with an older litex, updated litex, and all litepcie_util tests worked except the uart_test | 08:15 |
| sajattack[m] | after the update I mean, uart stopped working | 08:15 |
| sajattack[m] | maybe I'm forgetting some modification I needed for pcie uart to work | 08:16 |
| sajattack[m] | I was just getting no response over uart, which I guess could either be uart or bios problem? | 08:17 |
| _florent_ | sajattack[m]: Have you re-generated/recompiled the LitePCIe driver? Because the UART CSR mapping is maybe different with Rocket and could explain the behaviour is not updated correctly | 08:18 |
| sajattack[m] | yeah, I regenerated it multiple times, and rocket worked on one install of litex, and not another | 08:20 |
| _florent_ | if you have the build commands + working/failing version, I could have a look | 08:21 |
| sajattack[m] | I can try one more time, and make sure I wipe out the copy of litepcie_util I stashed in /usr/bin | 08:21 |
| sajattack[m] | yeah I'm not sure what the working version was unfortunately | 08:21 |
| sajattack[m] | it was just whatever I had last time I was messing around with litepcie | 08:21 |
| sajattack[m] | oh | 08:24 |
| sajattack[m] | it's in the .v file | 08:24 |
| sajattack[m] | fa5fd765 | 08:24 |
| sajattack[m] | but I made some modifications to comm_pcie and such | 08:25 |
| sajattack[m] | and litex_term, as documented here https://github.com/litex-hub/linux-on-litex-vexriscv/issues/249 | 08:26 |
| sajattack[m] | sajattack[m]: working version <- | 08:27 |
| sajattack[m] | non-working version f679992f8d7f53da2725752e0fb450be10959684 | 08:28 |
| sajattack[m] | ./sqrl_acorn.py --uart-name=crossover --with-pcie --build --driver --cpu-type=rocket --cpu-variant=linux | 08:31 |
| sajattack[m] | also tried --sys-clk-freq=50e6 and --sys-clk-freq=100e6 | 08:32 |
| _florent_ | ok thanks. | 08:33 |
| sajattack[m] | thank you | 08:33 |
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| cr1901 | _florent_: Wasn't meant to be a critique/nitpick, btw :). I just thought maybe it was there for a reason | 15:00 |
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| _florent_ | cr1901: Sure, it's just here to add an empty line after the heade :) but I should indeed change it. | 15:46 |
| cr1901 | _florent_: Actually, I think I might be confused myself... triple-quotes aren't raw strings? | 15:54 |
| cr1901 | meaning they still accept "\n" to put a newline in? | 15:55 |
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