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| Melkhior | 'lo | 10:57 |
|---|---|---|
| Melkhior | _florent_: trying to figure out a bug that I have, and I just saw this commment: https://github.com/enjoy-digital/litex/blob/70c5be6fb848d20cd20b590a69b246aad2092b24/litex/soc/interconnect/wishbone.py#L166 | 10:57 |
| Melkhior | what does it mean? It seems the 'register' parameter is True by default for SoC (https://github.com/enjoy-digital/litex/blob/70c5be6fb848d20cd20b590a69b246aad2092b24/litex/soc/integration/soc.py#L1014) | 10:58 |
| Melkhior | so I'm guessing it doesn't break that much :-) | 10:58 |
| Melkhior | TIA | 10:59 |
| Melkhior | (my design had a SBus -> Wishbone bridge, and occasionally my bridge returns a 'rerun' because it didn't receive a Wishbone ACK in time ; limit is 50 SBus cycles, or about 200 Wishbone cycles...) | 11:00 |
| Melkhior | (in about 0.5-2% of read accesses) | 11:01 |
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| jersey99 | Thanks sajattack[m] | 18:32 |
| jersey99 | I agree that it is super slow. | 18:33 |
| jersey99 | Another noob question: When using a litedram core, the default firmware/cpu code that gets loaded into the bios to run the dram calibration doesn't execute (essentially the bios doesn't boot) until I explicitly open the terminal. Is this intentional? If so, how to have it run automatically with a timer, say? | 18:45 |
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| cr1901 | The BIOS code waiting for you to open a terminal sounds specifically like a USB serial thing. If you are using a plain old UART, Idk what could be wrong | 20:37 |
| tpw_rules | i think the jtag uart has a buffer full flag the BIOS can spin on | 20:53 |
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