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| promach[m] | _florent_: I tried to grep for `PSCLK` and `psclk` , no result though. Are you using dynamic phase shift for litedram at all ? | 03:19 |
|---|---|---|
| promach[m] | and https://github.com/enjoy-digital/litedram/blob/master/litedram/phy/s6ddrphy.py does not seem to contain any instance of DCM module though | 03:24 |
| promach[m] | for context, see https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/spartan6_hdl.pdf#page=83 | 03:33 |
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| _florent_ | Wolf0: I would be happy to test your HBM memoru sandbox design on the FK33 (but at the end of the month) | 09:45 |
| _florent_ | promach[m]: The clocking is not done directly in the PHY, it's done in the target, ex: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/saanlima_pipistrello.py#L69-L104 | 09:47 |
| OmkarBhilare[m] | Hi _florent_ , | 09:57 |
| OmkarBhilare[m] | Just wanted to ask one question, I had produced a litex core with serv+litedram+wishbone port with the reference link you had given earlier. | 09:57 |
| OmkarBhilare[m] | In my case serv was initializing the sdram core after that I was trying to read sdram using wishbone, but it seems not working. I had tried different things. | 09:57 |
| OmkarBhilare[m] | I had set wb_cti to 3'b000 and wb_bte to 2'b00 and also wb_sel to 3'b111. | 09:59 |
| OmkarBhilare[m] | it was 32 bit address, data port. Everything until now I had done seems, right. | 09:59 |
| OmkarBhilare[m] | am I missing something in this case? | 09:59 |
| OmkarBhilare[m] | * I had set wb_cti to 3'b000 and wb_bte to 2'b00 and also wb_sel to 4'b1111. | 09:59 |
| OmkarBhilare[m] | it was 32 bit address, data port. Everything until now I had done seems, right. | 09:59 |
| OmkarBhilare[m] | am I missing something in this case? | 09:59 |
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| _florent_ | OmkarBhilare[m]: sorry I would need to have a closer look. It would probably be useful to do a simulation (with modified litex_sim or directly with Verilator) to understand what is miss-behaving, I would then be able to provide more specific help. | 10:12 |
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| promach[m] | _florent_: how do I generate the corresponding *pll_tuneable.v* from https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/saanlima_pipistrello.py#L69-L104 because I am facing issue using dynamic phase shift ? | 10:24 |
| * promach[m] posted a file: pll_tuneable.v (6KiB) < https://libera.ems.host/_matrix/media/r0/download/matrix.org/gfGywdXwigTfPcWULvgAvrCi > | 10:24 | |
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| promach[m] | _florent_: by the way, why are you using so many `CLKOUT`s , up to `CLKOUT5` ? | 11:22 |
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