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| simeonm | Hi! I'm trying to build a SOC for the Colorlight 5A-75B (v7) with both ethernet interfaces (liteeth etherbone on one and liteeth ethernet on the other). I am running into clock domain issues. I figured out I need to specify phy_cd, but now I get "ERROR: Cell 'TRELLIS_IO' cannot be bound to bel 'X0/Y38/PIOD' since it is already bound to cell 'TRELLIS_IO_1'". Here is what I've tried: https://gist.github.com/simeonmiteff/abe97d2e2904c5373919db4c2f56e46f, | 01:13 |
|---|---|---|
| simeonm | any ideas? | 01:13 |
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| david-sawatzke[m | The issue is that both phys share some pins like RESET MDIO & MDC, so any phy driver has to take that into account. You'll probably have to patch it or write your own phy driver | 14:15 |
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| leons | I think reset should be fine given it’s an output? For MDIO and MDC it might be fine to just not connect them if the PHY is properly configured on startup. | 16:44 |
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| simeonm | david-sawatzke[m, leons: ok thanks I'll look into that | 22:37 |
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