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| promach[m] | <promach[m] "and what do you mean by DRP inte"> _florent_: may I know if litedram is using DCM_SP or PLL_BASE settings for spartan-6 ? | 01:47 |
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| _florent_ | tnt: Congrats for Linux on iCE40, great work! Similar to your Doom port, I'm not sure the iCE40 designers were expecting this with their chip :) | 07:32 |
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| tnt | _florent_: Thanks :) Yeah, I'd love to see the iCE40 designers reactions ! For the doom port at least it was more reasonable and the speed is basically what I had to play back in the day on my not great 486. Here, it's pushing it a bit more so usefulness beyond demo is meh. But it shows you can do a lot with little if you try hard enough. | 07:54 |
| tnt | (And also, more importantly, this should settle once and for all "I wonder if you could run linux on it" questions) | 07:54 |
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| _florent_ | tnt: I also really liked your work on Doom, this a very good way to show that if you do things correctly and put enough efforts to it, lots of things are possible even with small FPGA! | 08:08 |
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| OmkarBhilare[m] | _florent_: thanks for the link, I have exposed the wb bus in my litexcore and also configured that wb bus to other logic of my code. | 08:58 |
| OmkarBhilare[m] | Just wanted to ask one thing if serv is initializing the SDRAM IP then on wishbone bus we can directly read or write, right? | 08:58 |
| OmkarBhilare[m] | (basically on wb bus do we need to do any initialization part?) | 08:58 |
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| OmkarBhilare[m] | * florent: thanks for the link, I have exposed the wb bus in my litexcore and also configured that wb bus to other logic of my code. | 09:05 |
| OmkarBhilare[m] | Just wanted to ask one thing if serv is initializing the SDRAM IP then on wishbone bus can we directly read or write, right? | 09:05 |
| OmkarBhilare[m] | (basically on wb bus do we need to do any initialization part?) | 09:05 |
| _florent_ | OmkarBhilare[m]: Once the SDRAM is initialized by your CPU, you can access the SDRAM from the Wishbone bus as a classical MMAPed peripheral | 09:23 |
| _florent_ | DerekKozel[m]: here is the bistream for the Acorn: https://github.com/litex-hub/litex-boards/files/6899443/sqrl_acorn_2021_07_29.zip | 09:26 |
| _florent_ | built and loaded with: python3 -m litex_boards.targets.sqrl_acorn --with-pcie --driver --build --load | 09:27 |
| _florent_ | I then just reboot the remote machine with the Acorn, copy the driver directory to it | 09:27 |
| _florent_ | cd kernel; make; sudo ./init.sh | 09:28 |
| _florent_ | dmes | 09:28 |
| _florent_ | dmesg | 09:28 |
| _florent_ | https://www.irccloud.com/pastebin/oB54YSvD/ | 09:28 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 09:28 |
| _florent_ | and then try user utilities | 09:28 |
| _florent_ | cd user; make | 09:28 |
| _florent_ | you can then try | 09:29 |
| _florent_ | ./litepcie_util info | 09:29 |
| _florent_ | ./litepcie_util scratch_test | 09:29 |
| _florent_ | ./litepcie_util dma_test | 09:29 |
| _florent_ | Without loading any software, the FPGA should be enumerated with lspci as: | 09:30 |
| _florent_ | 02:00.0 Memory controller: Xilinx Corporation Device 7024 | 09:30 |
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| DerekKozel[m] | Thanks! | 14:15 |
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| OmkarBhilare[m] | Hi _florent_ I was getting wrong values on wb bus, what should be the value of wb_sel? | 17:37 |
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| _florent_ | for a 32-bit bus, it should be 0b1111 | 18:02 |
| OmkarBhilare[m] | wb_bus = wishbone.Interface(data_width=16,adr_width=32) | 18:13 |
| OmkarBhilare[m] | with this the select line was 2 bit | 18:13 |
| OmkarBhilare[m] | I had tried 2'b00 and 2'b11, nothing seems work now | 18:14 |
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| cr1901 | tnt: I asked on fedi, but... is this Linux w/ MMU you booted on 5k? :o | 23:03 |
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