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| OmkarBhilare[m] | In litedram, In case of standalone generation can we control wishbone control and user port address and data width? | 11:53 |
|---|---|---|
| OmkarBhilare[m] | I have checked all the yml examples here, https://github.com/enjoy-digital/litedram/tree/master/examples | 11:53 |
| OmkarBhilare[m] | none of them used this, that's why I was asking. | 11:53 |
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| chiefwigms | any tips on how/what to debug w/ the ku+? i looked briefly at litescope but the doc is just a block diagram picture | 12:16 |
| chiefwigms | :) | 12:16 |
| _florent_ | chiefwigms: To use the bridges and LiteScope, you can have a look at: | 12:44 |
| _florent_ | https://github.com/enjoy-digital/litex/wiki/Use-Host-Bridge-to-control-debug-a-SoC | 12:44 |
| _florent_ | and https://github.com/enjoy-digital/litex/wiki/Use-LiteScope-To-Debug-A-SoC | 12:44 |
| _florent_ | If you have a UART, I would put a UARTBone bridge in the design, that would give you read/write access to the main bus of the SoC | 12:46 |
| _florent_ | https://github.com/enjoy-digital/litex/wiki/Use-Host-Bridge-to-control-debug-a-SoC#add-a-uart-bridge-to-your-soc | 12:46 |
| _florent_ | And then create CSR register in the design to probe value of internal signals (or just add a LiteScope instance) | 12:47 |
| _florent_ | for the KU/1000-baseX support, the first thing to look at are the initialization FSM, be sure that TX and RX are initialized correctly | 12:48 |
| _florent_ | then check the TX and RX frequencies (can be done with a simple counter running in TX/RX clock domains connected to a CSRStatus that is monitored every second through the bridge) | 12:49 |
| _florent_ | Sorry I've not been able to spend time on this yet, too much things to do :) | 12:50 |
| chiefwigms | k | 12:51 |
| _florent_ | OmkarBhilare[m]: For LiteDRAM standalone generation, it's not possible to control the data_width of the wishbone control interface | 12:52 |
| _florent_ | initial support has been added for user port data width, but it will probably only be available for the native interface | 12:52 |
| _florent_ | (for now) | 12:53 |
| OmkarBhilare[m] | <_florent_ "initial support has been added f"> Okay thanks | 12:57 |
| _florent_ | OmkarBhilare[m]: This has been added with https://github.com/enjoy-digital/litedram/pull/229 | 12:59 |
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| geertu_ | Anyone else seeing random corruptions with current litex-rebase? | 15:26 |
| geertu_ | The /etc/init.d/ scripts fail with weird errors | 15:27 |
| geertu_ | cat'ing the files show they're fine | 15:27 |
| geertu_ | executing them with "sh -v" shows the messed up content. | 15:27 |
| geertu_ | An older version based on v5.13-rc5 works fine, so I'm bisecting... | 15:28 |
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| somlo | geertu_: I am getting occasional invalid opcode kernel oops on rocket, but tracked it down to what is most likely timing failures in the ecp5 bitstream -- rebuilding the bitstream made the kernel stop crashing | 15:56 |
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| somlo | no idea what your underlying "hardware" is, but maybe rule that out first, before bisecting? | 15:57 |
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| blackpepper | After talking to somlo yesterday, I created a Fedora VM to try linux-on-litex-vexriscv. Now I am finally able to get "litex>" prompt at simulation. Thanks somlo for leading me to switch to Fedora! | 16:07 |
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| blackpepper | Now a question -- Does the simulation accept user keyboard input at "Litex>" prompt? Right now my simulation seems frozen at "Litex>" prompt. | 16:08 |
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| somlo | blackpepper: if everything goes well, you should be able to interact with your simulation via the prompt (sorry, can't help you any further, not a vexriscv user, and don't have access to my litex stuff at the moment) | 16:15 |
| somlo | blackpepper: also, unrelated to anything, you're disconnecting and re-connecting to this channel about once every 2 minutes -- just FYI :) | 16:16 |
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| geertu | somlo: we'll see... | 16:20 |
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| blackpepper | Thanks for letting me know I'm disconnecting at this channel. I'm using https://web.libera.chat/gamja/. I will search around how to keep connected to this channel. | 16:23 |
| tpb | Title: gamja IRC client (at web.libera.chat) | 16:23 |
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| blackpepper | I will drop from my laptop and reconnect from a remote VM to get better connection. | 16:34 |
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| geertu | somlo: Bisected to ca6eaaa210deec0e ("riscv: __asm_copy_to-from_user: Optimize unaligned memory access and pipeline stall") | 18:00 |
| geertu | which looks like an appropriate victim to blame | 18:00 |
| somlo | geertu: fair enough, as long as it doesn't go away if you rebuild the bitstream with a new nextpnr seed :P | 18:02 |
| somlo | I assume if you revert that commit things work fine for you once again? | 18:03 |
| geertu | Just tried a revert, works fine. "8*SZREG" looks like a sure disaster on 32-bit, as it will copy only half of the data | 18:04 |
| geertu | Doh, Günter already bisected a failure on rv32 qemu to that commit. | 18:05 |
| * geertu kicked Tsukamoto-san | 18:10 | |
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| somlo | so, unlike me, you found a bona fide regression... | 18:15 |
| geertu | somlo: You're using 64-bit rocket, right? | 18:15 |
| somlo | yeah | 18:15 |
| geertu | I knew it was working fine on my beagleV, so my first guess was an rv32 issue | 18:16 |
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| tcal | @xobs, mithro mentioned you might have created a way to easily specify a custom Vexriscv build, integrated with a Litex build? I know how to do one-off experiments by modifying the pythondata-cpu-vexriscv Makefile and/or the top sbt script and rebuilding a specific variant, or also how to add a new variant, but did you have another way? | 18:23 |
| somlo | gertu: I assume this will go away eventually (hopefully soon) if I keep rebasing the litex-rebase branch... | 18:25 |
| somlo | i.e., whatever fix for this regression will get applied upstream, and pulled into litex-rebase from there | 18:25 |
| geertu | somlo: Yep, I assume it will be fixed quickly upstream | 18:27 |
| mithro | tcal: https://github.com/enjoy-digital/litex/search?q=sbt | 18:33 |
| tcal | mithro: thanks! | 18:53 |
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