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| tweakoz | @Dolu - Is there an ETA for general Fpu and Amo support for mainline litex (for standard vexriscv, not vexriscv_smp) - I cannot get any soc to build with vexriscv_smp due to build errors. I also tried updating the VexRiscV repo in pythondata-cpu-vexriscv and I failed miserably there as well. I was able to build a verilog with the features directly from the current head of master of the VexRiscV using sbt - and I tried addin | 01:00 |
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| tweakoz | g my variant to litex's variant list and it tried to use it, but failed (due to version mismatches I am sure) - So what would be the easy quick and dirty way to get functional IMACFD (+AMO) RiscV32 support into a litex SOC ? | 01:00 |
| tweakoz | actually I only need IMAFD (+AMO) RiscV32 (I dont need compression) | 01:01 |
| tweakoz | I would like AMO - I want to use this: https://github.com/michaeljclark/riscv-atomics | 01:02 |
| tweakoz | @Florent - what basic testing do you need done before I submit a pull request for litex-boards ? - I have a couple of boards I have got working and would like to merge (Nexys4, CmodA7, and Mercury2) | 01:05 |
| tweakoz | And not just testing, are there any specific requirements you need met to accept new board submissions ? | 01:08 |
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| tweakoz | @Florent - I also have been working on a nanokernel based on top of litex bios / libbase that supports threads, memory allocation and other basics to get a minimal usable modern c++ system up. The nanokernel is itself written in c++ (because that is my native language and I work fastest in it) - I could port it to straight c after I work out a few of the issues - Is this something the litex repo would be interested in integ | 02:04 |
| tweakoz | rating as an optional firmware ? I myself decided for some projects I did not want the baggage of a full OS, but I wanted something a little more than litex bios offered. I could package it in a library and the user would just call a function in main() to transfer control to the nanokernel. | 02:04 |
| tweakoz | although maybe its not as useful for everyone - it is RiscV only.. to make everyone happy it would have to support all the CPU's | 02:05 |
| tweakoz | my little test program running on the nanokernel I think is about 40-60K of executable and runs fine even on a cmod-a7 - I am sure it would shrink a bit more if I ported to C. | 02:12 |
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| tweakoz_ | @Dolu - the error I get when attempting to use litex vexriscv_smp is "AttributeError: 'VexRiscvSMP' object has no attribute 'cluster_name'" | 08:32 |
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| promach[m] | Could anyone help with https://www.reddit.com/r/FPGA/comments/ocuruz/mpr_read_function_dependency_cycle_between/ ? | 10:40 |
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| _florent_ | tweakoz: Hi, if the boards you want to add to LiteX-Boards are able to run the basic LiteX SoC, you can consider it's OK to create a PR. | 21:13 |
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| _florent_ | tweakoz: For the nanokernel, that's definitely something interesting and I would be really curious to learn more about it. For now we are trying to keep software simple in LiteX, so not sure we could merge it directly, but that's clearly something we could encourage users to use if the have similar needs. | 21:17 |
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