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| jevinskie[m] | Thanks florent! I got packet sending working in the simulator. https://mobile.twitter.com/jevinskie/status/1406052471504478209 | 03:10 |
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| _florent_ | jevinskie[m]: good, thanks for the feedback. Would you mind creating an issue in LiteEth for the fifo_depth=None if you think something is broken? I'll look at it. | 07:21 |
| jevinskie[m] | Yup I’ll point out the issue. I’d give you a PR but $work has a terrible FOSS policy (even own time work requires sign off) | 08:10 |
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| jevinskie[m] | Thanks! https://github.com/enjoy-digital/liteeth/issues/69 | 08:34 |
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| _florent_ | Thanks jevinskie[m], I'll fix it next week | 10:37 |
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| tnt | Huh, has anyone tried a ice40 build recently ? | 19:04 |
| tnt | I'm trying ./1bitsquared_icebreaker.py on a fresh install and it's missing timing by a massive margin : Warning: Max frequency for clock 'main_crg_clkout': 10.85 MHz (FAIL at 24.00 MHz) | 19:05 |
| tnt | Naybe I'm misreading this but : https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/uart.py#L51 | 19:11 |
| tnt | Is that trying to implement a 64 bit adder ? | 19:11 |
| tnt | Definitely no hope to run that at 24 MHz on a UP5k. | 19:11 |
| tnt | I don't even get why tick is 32 bits to begin with. | 19:18 |
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| nickoe | Does verilator optimize signals away if not used? | 21:05 |
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