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| scientes | is there any example code that shows me how the cache-coherency of Zynq over AXI 4-stream works? | 00:11 |
|---|---|---|
| scientes | what I am thinking is that you would have memory-mapped cache lines, and you would read one, and the call an interrupt to wait for the other one to be filled, and then read that one and interrupt on the alternate one | 00:12 |
| scientes | but I want to see some code to better understand what is going on | 00:12 |
| scientes | it looks like ALL arm pheripherials are communicating with AXI | 00:13 |
| scientes | https://support.xilinx.com/s/article/1053914?language=en_US | 00:19 |
| scientes | Like it doesn't even saw how much data is in a packet | 00:19 |
| scientes | like I know DDR3---it is 32bytes x 2 | 00:20 |
| F4PGASlackBridge | <ept> In the F4PGA Architecture Definitions, readthedocs page, it looks like the link to the arch-defs github repo is broken. I would submit a pull request, but I’m not sure which repo to do that in | 00:47 |
| F4PGASlackBridge | <ept> (Unless the link is to a private repo, for some reason) | 00:49 |
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| F4PGASlackBridge | <pgielda> Yes the link is broken, it should be https://github.com/f4pga/f4pga-arch-defs | 09:23 |
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| F4PGASlackBridge | <ept> Great, thanks | 11:18 |
| F4PGASlackBridge | <ept> The repo organization between the Github pages for CHIPS Alliance and F4PGA are rather confusing. Is there a reason that yosys-f4pga-plugins, and f4pga-examples are under the CHIPS Alliance Github organization page and not the F4PGA Github organization page? Similarly, why does the F4PGA Github organization page include its own fork of the CHIPS alliance F4PGA repo? Shouldn’t it live exclusively in the F4PGA | 11:34 |
| F4PGASlackBridge | organization page? (maybe I’m completely wrong, but it seems pretty confusing as it is) | 11:34 |
| F4PGASlackBridge | <pgielda> Its complicated. A somewhat simplified explanation -- things in chipsalliance org have to be Apache 2.0 | 12:21 |
| F4PGASlackBridge | <pgielda> We're in a process of relicensing stuff but that takes time | 12:21 |
| F4PGASlackBridge | <pgielda> So for now some things live in f4pga org, think of it as a prolonged temporary situation | 12:22 |
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| F4PGASlackBridge | <ept> Ahh all right, that makes sense. Thank you for the explanation! | 15:06 |
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| cr1901 | umartinezcorral: Where did the fix_xc7_carry.py script go? https://github.com/f4pga/f4pga-arch-defs/commit/09b9a1d1f2db1778f1c9ad97f1a4725856ad3657 | 22:19 |
| cr1901 | ERROR: TCL interpreter returned an error: /home/william/Projects/FPGA/symbiflow/symbiflow-arch-defs/env/conda/envs/f4pga_arch_def_base/bin/python3: can't open file '/home/william/Projects/FPGA/symbiflow/symbiflow-arch-defs/utils/fix_xc7_carry.py': [Errno 2] No such file or directory | 22:19 |
| cr1901 | (ignore the symbiflow directory naming) | 22:19 |
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