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| lkcl | josuah, ok, the way it works is that to compile something to a bitstream you need two things: | 08:48 |
|---|---|---|
| lkcl | 1) some HDL | 08:48 |
| lkcl | 2) a constraints file | 08:48 |
| lkcl | the constraints file is what tells the nextpnr-$x to map individual NETLIST entries (pins) onto actual IO pads | 08:49 |
| lkcl | a differential clock is a clock line that, rather than having one single pin that goes on and off, there are a *pair* of clock lines that, simultaneously, switch to the opposite direction | 08:50 |
| lkcl | i.e. they are "differential" | 08:50 |
| lkcl | the convention to distinguish differential pair pins is, one ends with "P" the other ends with "N" | 08:51 |
| lkcl | so | 08:51 |
| lkcl | ClockP | 08:51 |
| lkcl | ClockN | 08:51 |
| lkcl | P for Positive, N for Negative | 08:51 |
| lkcl | back to internal blocks | 08:53 |
| lkcl | yosys does *not* know about constraints (the IO pads), it only knows about NETLISTs and the things that those nets connect to. | 08:54 |
| lkcl | but | 08:54 |
| lkcl | you do have to have some sort of representation of e.g. the IBUFDS, as a black-box module, with the inputs and outputs, so that when the *use* of that module is passed over to nextpnr-$x (or VTR), the PnR tool knows what to do with it | 08:55 |
| lkcl | ok so here's a declaration - a model - of IBUFDS | 08:57 |
| lkcl | https://electronics.stackexchange.com/questions/93373/how-to-route-a-lvds-clock-from-fpga-input-to-output | 08:57 |
| tpb | Title: vhdl - How to route a LVDS clock from FPGA input to output? - Electrical Engineering Stack Exchange (at electronics.stackexchange.com) | 08:57 |
| lkcl | so, now you can (after probably translating that to verilog) use an IBUFDS / OBUFDS as if it was some sort of "black box". | 08:58 |
| lkcl | you *do not* have to write the *contents* of that black box named IBUFDS / OBUFDS: just use it (as an external module) | 08:59 |
| lkcl | yosys is intelligent enough to recognise this and will not complain (or, it shouldn't). it will simply pass through the black box - and all its netlists - IBUFDS.I, IBUFDS.IB, IBUFDS.O - to nextpnr-$x / VTR | 09:00 |
| lkcl | nextpnr-$x / VTR will go, "oh, you wanted an IBUFDS, and you're compiling for ICE40? sure, i recognise those, let me just wire that up and P&R it for you" | 09:01 |
| lkcl | so it's actually extremely straightforward | 09:01 |
| lkcl | the only tricky bit, as you're finding out, is that none of this direct-interfacing with FPGA blocks is really properly documented, you're pretty much just expected to "work it out" | 09:03 |
| lkcl | sometimes not even the FPGA designers properly provide documentation, one good example is the Lattice ECP5 JTAG block, which allows you to tap into the JTAG port and insert your own commands so that you can interact with openocd via the ECP5's JTAG port | 09:04 |
| lkcl | someone had to actually reverse-engineer the ECP5's JTAG block | 09:04 |
| lkcl | but, your first priority is to find the "model" of the ICE40 IBUFDS. | 09:05 |
| lkcl | the one i found above i just saw it's for Xilinx FPGAs (sigh) despite (sigh) searching on gooogle "ICE40 IBUFDS". getting really irritating that google "helpfully" puts in additional unrelated searches to the keywords | 09:06 |
| lkcl | sources where you should definitely find a model file (IBUFDS.v and/or IBUFDS.vhdl) will be in the Lattice (proprietary) SDK | 09:07 |
| lkcl | beyond that, you're into playing the "hunt the unknown reverse-engineered thing on the internet" game. | 09:08 |
| tnt | No such thing as IBUFDS in an ICE40. It's SB_IO | 09:20 |
| josuah | lkcl: great overview, thank you | 10:38 |
| * josuah takes a cup of tea and reads | 10:38 | |
| josuah | lkcl: that confirms what I was supposing, thank you for providing me that ground | 12:11 |
| josuah | there might be a way to get around the name of what to search through the vendor's documentation | 12:11 |
| josuah | for ICE40 and SB_IO (thanks tnt): https://www.latticesemi.com/~/media/LatticeSemi/Documents/Handbooks/iCE40FamilyHandbook.pdf#page=152 | 12:14 |
| josuah | that makes a starting point to search in the meantime it gets better | 12:14 |
| josuah | @amuttur if you are still around: https://www.latticesemi.com/~/media/LatticeSemi/Documents/Handbooks/iCE40FamilyHandbook.pdf#page=152 -> Using Differential I/O | 12:25 |
| josuah | that could be what you need if your board is the iCE40... | 12:25 |
| josuah | lkcl: may I quote what you said? It could be useful to some. | 12:26 |
| josuah | lkcl: anonymously or not as you would prefer | 12:27 |
| josuah | https://josuah.net/blog/1652358092/ <- I reworded slightly ('s -> is and alike for chat -> article conversion) | 12:43 |
| tpb | Title: josuah.net (at josuah.net) | 12:43 |
| lkcl | sure, no problem. do put a link to the irclogs - both i and mithro run irclog2html... 1 sec... | 14:24 |
| lkcl | https://libre-soc.org/irclog-f4pga/%23f4pga.2022-05-12.log.html#t2022-05-12T11:38:10 | 14:26 |
| tpb | Title: Thursday, 2022-05-12 (at libre-soc.org) | 14:26 |
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| josuah | lkcl: thank you! changed on my side. | 14:49 |
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| lambda | Hi, did something in the build pipeline for the prebuilt f4pga-arch-defs files break? Unfortunately I can't look at https://storage.cloud.google.com/symbiflow-arch-defs-gha/ at all without a google account, but https://storage.googleapis.com/symbiflow-arch-defs-gha/symbiflow-toolchain-latest, which I've been using so far, points to a build from March. | 16:01 |
| tpb | Title: Anmelden – Google Konten (at storage.cloud.google.com) | 16:01 |
| F4PGASlackBridge | <amuttur> @josuah Thank you! My board is from Xilinx though. I can implement the differential clock on Vivado, but I wanted to see if someone did it on F4PGA cause I couldn't find a lot of documentation about it | 16:09 |
| lkcl | amuttur: ah! then that link i found above *is* relevant :) | 16:12 |
| lkcl | which FPGA is it? | 16:12 |
| lkcl | you should be able to extract the following from the vivado compilation: | 16:13 |
| lkcl | 1) the verilog model for IBUFDS.v | 16:14 |
| lkcl | 2) the constraints file (.xcf? something like that) | 16:14 |
| lkcl | 3) if you used some sort of wizard, at least it will have created the verilog source *using* an IBUFDS instance which you can cut/paste out | 16:16 |
| lkcl | basically you have to do everything as text files / source-code files, so need to know a little bit more about how symbiflow / nextpnr-xilinx actually work | 16:16 |
| lkcl | which board and which FPGA are you using? | 16:17 |
| F4PGASlackBridge | <amuttur> I'm using the AC 701 evaluation kit from Xilinx, it's Artix-7 series | 17:02 |
| F4PGASlackBridge | <amuttur> Yup, I used the clk_wiz.v verilog instantiation, but F4PGA has trouble understanding the IBUFDS cell | 17:02 |
| F4PGASlackBridge | <umartinezcorral> @mliberty could you get it to work? | 17:36 |
| F4PGASlackBridge | <mliberty> I think I know how to make it work but haven't had a chance yet to try it out. I'll ping you if I need more help. Thanks! | 17:37 |
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| F4PGASlackBridge | <amuttur> ```# Building complex block graph # Building complex block graph took 0.06 seconds (max_rss 71.0 MiB, delta_rss +0.0 MiB) # Load circuit # Load circuit took 0.00 seconds (max_rss 71.0 MiB, delta_rss +0.0 MiB) Error 1: Type: Blif file File: top.eblif Line: 639 Message: Failed to find matching architecture model for 'IBUFDS'``` | 19:12 |
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