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| F4PGASlackBridge | <eddy.gta17> I have access to an NI myRio board which uses the Xilinx Zynq-7010. Would it be a futile attempt in trying to run the toolchain on this board, since it is not supported by F4GPA? | 04:54 |
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| F4PGASlackBridge | <eddy.gta17> Going quickly through the documentation I see that the Zybo Z7 board also uses the same chip. | 04:57 |
| F4PGASlackBridge | <eddy.gta17> https://f4pga.readthedocs.io/projects/arch-defs/en/latest/getting-started.html The repository mentioned here needs authentication. | 05:20 |
| tpb | Title: Getting Started with F4PGA Toolchain development — F4PGA Architecture Definitions latest documentation (at f4pga.readthedocs.io) | 05:20 |
| F4PGASlackBridge | <kgugala> I think that one wasn't moved to chips alliance org yet | 06:29 |
| F4PGASlackBridge | <kgugala> You can try https://github.com/SymbiFlow/f4pga-arch-defs | 06:30 |
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| marzoul | @eddy.gta17 I am interested in seeing that done too :-) I will use a Zybo Z7. When I have enough time. Currently thinking all the details in terms of setup... | 22:12 |
| marzoul | @eddy.gta17 For example, my main question is, what bits do we have to take care of in the bitstream part, so that (re)programming the FPGA does not shut off the CPUs in the process ? More generally identifying config bits that are set in bitstream part and those set in cpu program part or whatever accessible through jtag that is not bitstream.. | 22:16 |
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