Saturday, 2022-03-05

*** tpb <[email protected]> has joined #f4pga00:00
*** marzoul <[email protected]> has quit IRC (Ping timeout: 240 seconds)00:03
*** cr1901_ <cr1901_!~cr1901@2601:8d:8600:911:cf1:8507:720a:c17> has quit IRC (Remote host closed the connection)15:58
*** cr1901_ <cr1901_!~cr1901@2601:8d:8600:911:cf1:8507:720a:c17> has joined #f4pga15:58
*** cr1901_ is now known as cr190115:59
*** marzoul <[email protected]> has joined #f4pga19:02
marzoulHi20:38
marzoulI have started a very casual attempt at adding Virtex-7 devices to prjxray.20:38
marzoulWhere : branch virtex7 in fork https://github.com/marzoul/prjxray20:38
marzoulThere is no intention of building a clean and structured patch, it is more unorganized changes that I did in order to make existing fuzzers go as far as possible before a fail is reached.20:38
marzoulThe goal is more to identify the significant differences that support of Virtex-7 would bring compared to current prjxray.20:38
marzoulObviously some of the changes share same goals of independent efforts to support Kintex-7.20:39
marzoulSummary of changes needed :20:40
marzoul- some parts have unbonded IOs / PADs even in largest known package, so iterating over pad names in Vivado will not enumerate all IOBs20:40
marzoul- some IOBs might be bonded to different pad names depending on package ? why not, would need a check20:40
marzoul- some parts do NOT have low-perf pins, only high-perf, so default design generation must be adapted on many fuzzers, along with other device parameters20:40
marzoul- PCIe fuzzers are not designed to handle multiple PCIe sites20:40
marzoul- transceivers are GTXE2, not GTP, need tweaking20:40
marzoulDoing these hacks, I realized that the following directions could be of interest for prjxray :20:44
marzoul- GTXE2 vs GTP could be detected from database itselt (there will be GTH also at some point) - alternatively, define an env var in settings/xx.sh to enable the right fuzzers20:44
marzoul- number of specimens in fuzzers could/should be based on number or primitives of interest in device20:44
marzoulFinal note : This is very casual hacks on spare computer time. Also I have no broad of fundamental understanding of current prjxray project as a whole, so these attempts are also a means for me to progress. So will be no fast progress on this - and anybody is welcome to take and improve on what I did (or throw it all away and start over xD).20:48
marzoulNote : Using make with options -j10 MAX_VIVADO_PROCESS=420:52
marzoulFuzzer000 succeeded20:52
marzoulFuzzer075 succeeded after 23 sec20:52
marzoulFuzzer001 succeeded after 2 min20:52
marzoulFuzzer073 succeeded after 4 min 20 sec20:52
marzoulFuzzer005 fails after 1h50 - 2h20:52
marzoulFuzzer072 succeeded after 24-25h20:52
marzoulFuzzer074 not started (started after 005)20:52
marzoulmax mem 30.1 GB, reached during fuzzers 005 + 0720:52
marzoulNote : fuzzer005 fails at the end, when making database, with following error:20:54
marzoulTraceback (most recent call last):20:54
marzoul    main()20:54
marzoul  File "/home/prostboa/Projets/projet-prjxray/prjxray/fuzzers/005-tilegrid/add_tdb.py", line 162, in main20:54
marzoul    run(args.fn_in, args.fn_out, verbose=args.verbose)20:54
marzoul  File "/home/prostboa/Projets/projet-prjxray/prjxray/fuzzers/005-tilegrid/add_tdb.py", line 145, in run20:54
marzoul    localutil.add_tile_bits(20:54
marzoul  File "/home/prostboa/Projets/projet-prjxray/prjxray/fuzzers/005-tilegrid/util.py", line 111, in add_tile_bits20:54
marzoul    assert offset + words <= 101, (20:54
marzoulAssertionError: ('CMT_TOP_L_UPPER_T_X250Y148', 125, 98, 27, 'CLB_IO_CLK')20:54
marzoul( I'm finished for these flood messages now ;-)  )20:54
*** marzoul2 <[email protected]> has joined #f4pga22:12
*** marzoul <[email protected]> has quit IRC (Ping timeout: 272 seconds)23:19

Generated by irclog2html.py 2.17.2 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!