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| rowang077[m] | Hello everyone | 16:21 |
|---|---|---|
| rowang077[m] | I'm making a small SDR SDRAM controller that will run on ECP5 FPGA. | 16:21 |
| rowang077[m] | is it possible somehow to constrain the clock that goes to the SDRAM module and the clock that goes to the controller are out of phase slightly? I can generate out of phase clocks with ecppll but how can I apply the appropriate constraints? | 16:23 |
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