| *** tpb has joined #yosys | 00:00 | |
| *** Degi_ has joined #yosys | 00:02 | |
| *** Degi has quit IRC | 00:03 | |
| *** Degi_ is now known as Degi | 00:03 | |
| *** citypw has joined #yosys | 01:13 | |
| *** sm2n has joined #yosys | 01:44 | |
| *** citypw has quit IRC | 02:19 | |
| *** Degi_ has joined #yosys | 04:01 | |
| *** Degi has quit IRC | 04:02 | |
| *** Degi_ is now known as Degi | 04:03 | |
| *** captain_morgan has quit IRC | 06:09 | |
| *** captain_morgan has joined #yosys | 06:10 | |
| *** danvet has joined #yosys | 06:50 | |
| *** kraiskil has joined #yosys | 06:52 | |
| *** kraiskil has quit IRC | 07:30 | |
| *** kraiskil has joined #yosys | 08:22 | |
| *** kraiskil has quit IRC | 08:31 | |
| *** citypw has joined #yosys | 10:51 | |
| *** kraiskil has joined #yosys | 12:02 | |
| *** ayazar1 has joined #yosys | 12:14 | |
| *** kraiskil has quit IRC | 12:26 | |
| *** citypw has quit IRC | 14:48 | |
| *** GenTooMan has quit IRC | 14:53 | |
| *** vidbina has joined #yosys | 14:56 | |
| *** tautologico has joined #yosys | 15:15 | |
| *** GenTooMan has joined #yosys | 15:26 | |
| *** tautologico has quit IRC | 16:22 | |
| jophish1 | Hi all | 17:09 |
|---|---|---|
| jophish1 | I have some generated systemverilog code and yosys doesn't seem to like it very much | 17:09 |
| jophish1 | It seems to choke here: https://gist.github.com/expipiplus1/a412cffa9a752a52eb7859f0390f6008#file-hdmi_types-sv-L44 | 17:10 |
| jophish1 | on `function` | 17:10 |
| jophish1 | Specifically: `.build/clash/HDMITop.topEntity/hdmi_types.sv:44: ERROR: syntax error, unexpected TOK_FUNCTION` | 17:10 |
| jophish1 | I don't know enough about SV to really be able to tell where the issue is | 17:11 |
| FL4SHK | jophish1: you're using SV with yosys? Really? | 17:14 |
| jophish1 | oh, is this not a cool thing to do? | 17:14 |
| FL4SHK | try sv2v if you want to use SV with yosys | 17:14 |
| FL4SHK | yosys's SV support is very poor | 17:14 |
| jophish1 | I was using it because I have SV assertions set up | 17:14 |
| FL4SHK | ah | 17:15 |
| FL4SHK | that's valid | 17:15 |
| FL4SHK | if you're just using assertions, yosys is actually still limited, but it does support enough of that to get the job done | 17:15 |
| jophish1 | although they're generated too, so I could probably set up a Verilog backend for them too | 17:15 |
| FL4SHK | I'm building something intended for use with yosys for formal | 17:15 |
| FL4SHK | it's a DSL to generate a VHDL AST | 17:16 |
| FL4SHK | combined with the GHDL synthesis plugin, this should handle my needs in a language | 17:16 |
| jophish1 | hehe, I had no end of trouble using GHDL for this! | 17:17 |
| * jophish1 uploaded a video: (11047KiB) < https://matrix.monoid.al/_matrix/media/r0/download/monoid.al/AznMjvyGWWJdSeqEScUOulQQ/VID_20210510_015454.mp4 > | 17:55 | |
| jophish1 | Worked first time! Thanks yosys :) | 17:56 |
| *** roamingr1 has joined #yosys | 18:13 | |
| *** kraiskil has joined #yosys | 18:57 | |
| *** kraiskil has quit IRC | 19:11 | |
| *** ayazar1 has quit IRC | 19:15 | |
| *** ayazar1 has joined #yosys | 19:16 | |
| *** roamingr1 has quit IRC | 19:17 | |
| *** vidbina has quit IRC | 19:18 | |
| *** vidbina has joined #yosys | 20:43 | |
| *** ayazar1 has quit IRC | 20:43 | |
| *** danvet has quit IRC | 21:49 | |
| *** lf has quit IRC | 23:08 | |
| *** lf has joined #yosys | 23:08 | |
| *** roamingr1 has joined #yosys | 23:21 | |
| *** vidbina has quit IRC | 23:49 | |
Generated by irclog2html.py 2.17.2 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!