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| justchen1369 | hello | 18:37 |
|---|---|---|
| Degi | hi | 18:38 |
| justchen1369 | could you send me a link to the latest manual? | 18:38 |
| Degi | Oh, the official URL at http://yosyshq.net/yosys/files/yosys_manual.pdf seems to be broken, a version from last year is here https://github.com/YosysHQ/yosyshq.github.io/blob/master/yosys/nogit/manual/manual.pdf otherwise you can probably just compile this https://github.com/YosysHQ/yosys/tree/master/manual | 18:42 |
| justchen1369 | thanks! | 18:42 |
| justchen1369 | another question | 18:43 |
| justchen1369 | why is the latest release a year old? | 18:43 |
| Degi | Hm, there seems to be about a release every year, though occasionally two years without one... If you want the newest features usually downloading the git repo and building it yourself is the best way | 18:44 |
| justchen1369 | thanks | 18:52 |
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| justchen1369 | how might I convert a verilog file into a json logical gate representation, using only AND, OR, and NOT? | 20:00 |
| gatecat | justchen1369: something like synth; abc -g AND,OR; write_json out.json | 20:41 |
| gatecat | (note that NOT is implicit in the list of gates passed to abc) | 20:42 |
| justchen1369 | alright I'll try that, thanks! | 20:44 |
| justchen1369 | seems to be spitting a bunch of debug info into the file | 20:49 |
| gatecat | you could try setattr -unset src * before write_json | 20:56 |
| gatecat | but otherwise, for the most part whatever is parsing the json should just ignore the attributes section, then it shouldn't matter anywau | 20:57 |
| gatecat | *anyway | 20:57 |
| justchen1369 | in netnames, does "bits" correspond with each logic gate's "name"? | 21:00 |
| justchen1369 | by which I mean id | 21:01 |
| justchen1369 | it looks like | 21:07 |
| justchen1369 | "$abc$113$add$counter.v:6$2_Y[0]": { | 21:07 |
| justchen1369 | "hide_name": 1, | 21:07 |
| justchen1369 | "bits": [ 9 ], | 21:07 |
| justchen1369 | "attributes": { | 21:07 |
| justchen1369 | } | 21:07 |
| justchen1369 | }, | 21:07 |
| gatecat | yeah, it means bit 9 used elsewhere corresponds to that net (not logic gate) name | 21:10 |
| justchen1369 | ah | 21:14 |
| justchen1369 | so bit-by-bit input/output | 21:14 |
| justchen1369 | it seems to be provided in the ports property; can I ignore the netnames? | 21:17 |
| justchen1369 | I'm honestly quite confuse | 21:21 |
| justchen1369 | d | 21:21 |
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