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| promach3 | yosys does not support $ceil ? | 02:48 |
|---|---|---|
| promach3 | yosys has the following error for https://github.com/promach/DDR/blob/main/ddr3_memory_controller.v#L1061 | 02:52 |
| promach3 | ERROR: Found error in internal cell \ddr3_memory_controller.$ge$ddr3_memory_controller.sv:1061$73 ($ge) at kernel/rtlil.cc:991: | 02:52 |
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| mwk | promach3: well you found a bug | 10:17 |
| mwk | https://github.com/YosysHQ/yosys/issues/2718 | 10:17 |
| mwk | as a workaround, I think assigning the constant to an intermediate const-valued wire would help | 10:18 |
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| promach3 | mwk: what do you mean by **intermediate** const-valued wire ? | 11:10 |
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| mwk | promach3: actually now that I look at it, I think the comparison isn't synthesizable verilog in the first place | 11:49 |
| * promach3 < https://matrix.org/_matrix/media/r0/download/matrix.org/bvPlxqpuksYtjrBbBfnxTjad/message.txt > | 11:50 | |
| mwk | because it involves a floating point comparison | 11:50 |
| promach3 | yup, your suggested countermeasure also does not work | 11:50 |
| promach3 | <mwk "because it involves a floating p"> I suppose this is also a bug ? | 11:51 |
| mwk | and the proper fix would be to write "localparam [31:0] TIME_TRFC = $ceil(...);" | 11:51 |
| mwk | so that it'll be cast to integer | 11:51 |
| mwk | no, this is not a bug | 11:51 |
| mwk | it's just that floating point operations are not synthesizable | 11:51 |
| mwk | because they don't map to logic circuits without major effort | 11:52 |
| promach3 | you mean add `[31:0]` ? | 11:52 |
| mwk | yes | 11:52 |
| promach3 | let me try | 11:52 |
| mwk | and btw by intermediate wire I meant something like "wire [31:0] tmp = 2.0; assign O = A < tmp;" | 11:54 |
| mwk | but adding the type directly on localparam is superior | 11:54 |
| promach3 | ok, cool thanks mwk | 11:56 |
| promach3 | mwk: ok, now I could pass yosys check without errors. How do I pass yosys synthesis result to Xilinx ISE for place-and-route for Spartan-6 ? | 12:02 |
| mwk | there's an example in yosys tree | 12:03 |
| mwk | https://github.com/YosysHQ/yosys/tree/master/examples/mimas2 | 12:03 |
| mwk | you'll need to write your own UCF of course, but the same synthesis script should work | 12:04 |
| mwk | (well, that and fix the part number) | 12:04 |
| promach3 | ok, thanks mwk | 12:17 |
| promach3 | mwk: are you familiar with DDR ? May I ask some advice on setting constraints for `DQ` and `DQS` signals ? | 12:25 |
| promach3 | they are both `inout` signals | 12:26 |
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| promach3 | ok, found https://www.cnblogs.com/lelin/p/12652460.html | 14:45 |
| tpb | Title: DDR接口时序实例 - 春风一郎 - 博客园 (at www.cnblogs.com) | 14:45 |
| promach3 | mwk: Why the example you had given just now does not include SDC constraint file ? | 16:08 |
| mwk | this is xilinx ISE, you generally use UCF constraints | 16:15 |
| mwk | or at least they were enough for my little example | 16:15 |
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