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| Paul1 | hello, i've got a question about using the additional inverted output pin in flip flops, the FAQ states "There is limited support for FFs with non-inverted and inverted outputs in Yosys" | 15:57 |
|---|---|---|
| Paul1 | i'm getting very weird results when i try to add these outputs to my library, minimal example here: https://paste.sh/YM68EEkE#SBhprH09QeQSULWku_zlfj0R | 15:58 |
| tpb | Title: paste.sh · encrypted pastebin (at paste.sh) | 15:58 |
| Paul1 | and this is the graphviz output that I get: https://paste.sh/XBuQV90X#2IM8mKGbc51DYAuwKwx2p9w0 | 15:58 |
| tpb | Title: paste.sh · encrypted pastebin (at paste.sh) | 15:58 |
| Paul1 | note how there are only 2 flip flops for a 3 bit counter and Qn is shown as in input and there's a weird new signal that is used as an input but not driven by anything...? | 16:00 |
| Paul1 | i'm confused, what am I doing wrong? | 16:00 |
| Paul1 | everything works when i remove the IQN output from the ff in my library | 16:00 |
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| Twix | You only have 2 flip flops because you use 2 bits in your counter. The third bit is not used. So it implements it using two flip flops(You are wrapping instant from 4 to 0. So you only have 4 states) | 17:26 |
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| Paul1 | no, this thing has 5 states, it wraps to 0 *after* the cycle where it's set to 4. the code basically sets zero = true for one cycle, then waits 4 cycles and repeat | 18:55 |
| Paul1 | it does the right thing if i just remove the IQN output pin in the library which isn't needed anyways | 18:55 |
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| Paul1 | found it: output was named "QN" in cells.lib and "Qn" in cells.v | 20:08 |
| Paul1 | feature request: make this fail early and hard | 20:08 |
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| Lofty | Paul1: unfortunately I'm pretty sure failing there is a violation of the Verilog standard | 21:29 |
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