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| Forty-Bot | how do the multiple outputs for SB_PLL40_2F_CORE work? | 15:35 |
|---|---|---|
| Forty-Bot | are they the "core" and "global" outputs e.g. as seen in https://imgur.com/7qBZ5IT.png | 15:36 |
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| Forty-Bot | or does each port have duplicated hardware for the phase shifter and fine delay adjustment port? | 15:39 |
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| agg | you get PLLOUTGLOBALA, PLLOUTCOREA, PLLOUTGLOBALB, PLLOUTCOREB | 15:47 |
| agg | there's only one fine delay adjust aiui, but you can choose 0/90 phase shift or half-freq for the second port | 15:50 |
| agg | you get PLLOUT_SELECT_PORT{A,B} each of which can be SHIFTREG_0deg, SHIFTREG_90deg, GENCLK, or GENCLK_HALF | 15:51 |
| Forty-Bot | ok, so if I change the fine delay adjust then only (e.g.) port A gets adjusted? | 15:51 |
| agg | FDA_RELATIVE delays output A relative to output B, for finer phase between them | 15:51 |
| Forty-Bot | ah | 15:52 |
| agg | I've not tried FDA with two outputs though, have only used two outputs to get a half-freq or a 90' phase | 15:52 |
| agg | this is all in the SBTICETechnologyLibrary201701.pdf | 15:53 |
| agg | it doesn't have a diagram, which would have been helpful, but the explanation of what the parameters do is updated for the 2F PLLs | 15:53 |
| Forty-Bot | yeah, I saw that which is what I was confused | 15:53 |
| Forty-Bot | since the diagrams in the pll design guide only show one port | 15:53 |
| agg | the pll design guide has only the most passing reference to the idea it can output two frequencies, lol | 15:56 |
| agg | it says "If a two-port | 15:56 |
| agg | PLL is used, this additional delay is applied only on Port A. | 15:56 |
| agg | and nowhere else mentions the concept of a two-port PLL or a port B existing, lol | 15:56 |
| Forty-Bot | it also mentions them in the signals section | 16:01 |
| Forty-Bot | but doesn't clarify that firther | 16:01 |
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