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| emeb | I'm having some trouble with yosys synthesizing incorrectly with the SB_MAC16 cells on ice40 ultra. I'm trying to build a linear interpolator that requires two multiplies followed by an add and yosys appears to be failing when it tries to merge the addition into one of the SB_MAC16 cells. | 15:50 |
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| emeb | What I see is that one of operands of the add ends up being flagged as unused and all the logic upstream of that is then removed. If I set that adder input as another output of the module then the upstream logic is preserved, but the final sum is incorrect. | 15:53 |
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| emeb | I've made an MCVE of the issue here -> https://pastebin.com/hvcUuKT2 | 16:08 |
| tpb | Title: // mac_test.v - demonstrate SB_MAC16 synth bug// 03-21-21 E. Brombaugh`def - Pastebin.com (at pastebin.com) | 16:08 |
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| emeb | Looking at the verilog output from yosys I can see that the m0 term is not being hooked up to the C & D inputs of the second SB_MAC16 cell. I was able to copy/paste those instantiations into my code, hook up the C & D inputs and everything works. | 17:16 |
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