Friday, 2021-03-19

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develonepi3Hello I have a toplevel_pll.v for iCE40HX8K-EVB.  This board has 100MHz clock.  is there a way to find what desired freq was used?14:56
develonepi3Hello All; This is "https://github.com/develone/VexRiscv/blob/master/Murax-Catboard/toplevel_pll.v" file in question.  I have HX8K which has a clock 100MHz.14:59
Twixyou can just calculate the frequency the PLL will output14:59
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develonepi3Twix: icepll -i 100 -o 12 Error: PLL output frequency 12.000 MHz is outside range 16 MHz - 275 MHz! See "https://github.com/develone/VexRiscv/blob/master/Murax-Catboard/pllcalc.xls"16:19
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Twixah now i understand, you are asking how to get the 12 MHz from 100 MHz input?16:26
Twixone way would be to use the PLL generate a higher frequency(e.g. 24 MHz) and divide it inside your logic. You could use a counter for that16:27
develonepi3Twix I have a toplevel_pll.v which has the DIVR, DIVF, and DIVQ. "https://github.com/develone/VexRiscv/blob/master/Murax-Catboard/toplevel_pll.v"16:29
develonepi3Twix This is for iCE40/iCE40HX8K-EVB which has 100MHz like the my target HX8K.16:30
tnt... don't divide in logic unless you have no choice.16:33
tnthere you do : You can use the post divide by 2 of the PLL.16:33
tntSee `GENCLK_HALF`16:33
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develonepi3tnt The file already has GENCLK.17:14
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develonepi3tnt & Twix this is to run Murax Risc-V on a HX8K written scala.17:17
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lambdaanother question about SV types: is this expected behaviour? typedefs apply to the entire scope they are in, no matter their position, yet parsing requires the type to be defined as *anything* before it's used as an identifier https://bpa.st/33YQ19:24
tpbTitle: View paste 33YQ (at bpa.st)19:24
lambdaif the first line is removed, it doesn't parse anymore, even though that type signature is never actually used19:25
gatecatI do remember reading they must be defined before they are used. I suspect t3 should be 8bit but it's been over a year since I looked19:30
lambdaalright, LRM reading time it is19:47
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