| *** tpb has joined #yosys | 00:00 | |
| *** adjtm_ has joined #yosys | 00:11 | |
| *** adjtm has quit IRC | 00:13 | |
| *** adjtm_ has quit IRC | 00:28 | |
| *** unkraut has joined #yosys | 00:31 | |
| *** FFY00_ has joined #yosys | 00:33 | |
| *** kristianpaul has quit IRC | 00:41 | |
| *** kristianpaul has joined #yosys | 00:42 | |
| *** lf has quit IRC | 00:58 | |
| *** lf has joined #yosys | 00:58 | |
| *** citypw has joined #yosys | 02:51 | |
| *** Degi has quit IRC | 03:11 | |
| *** Degi has joined #yosys | 03:14 | |
| *** citypw has quit IRC | 04:31 | |
| *** citypw has joined #yosys | 06:19 | |
| *** jfcaron has quit IRC | 06:32 | |
| *** craigo has joined #yosys | 06:50 | |
| *** kraiskil has joined #yosys | 07:03 | |
| *** emeb_mac has quit IRC | 07:10 | |
| *** s_frit has quit IRC | 07:36 | |
| *** s_frit has joined #yosys | 07:36 | |
| *** kraiskil has quit IRC | 07:51 | |
| *** vidbina_ has joined #yosys | 08:54 | |
| *** citypw has quit IRC | 09:27 | |
| *** vidbina_ has quit IRC | 09:30 | |
| *** vidbina_ has joined #yosys | 09:51 | |
| *** vidbina_ has quit IRC | 10:25 | |
| *** mancaus_ has joined #yosys | 10:35 | |
| *** mancaus has quit IRC | 10:37 | |
| *** _whitelogger has quit IRC | 11:54 | |
| *** _whitelogger has joined #yosys | 11:56 | |
| *** mancaus_ has quit IRC | 12:15 | |
| *** mancaus_ has joined #yosys | 13:25 | |
| *** s_frit has quit IRC | 13:29 | |
| *** s_frit has joined #yosys | 13:30 | |
| * promach3 uploaded an image: image.png (286KiB) < https://matrix.org/_matrix/media/r0/download/matrix.org/KnGEMsmjyvKgmKVluzBwmBfW/image.png > | 14:03 | |
| promach3 | Why `BB_dq` is not part of design ? | 14:03 |
|---|---|---|
| promach3 | https://gist.github.com/promach/2c477b1dbc39f04a1271fb229e6d678c#file-ddr3_memory_controller-v-L245-L251 | 14:04 |
| *** vidbina_ has joined #yosys | 14:26 | |
| promach3 | it is located here : https://github.com/YosysHQ/yosys/blob/master/techlibs/ecp5/cells_io.vh#L10 , but how do I actually instantiate this special module ? | 14:31 |
| Lofty | promach3: that module just wraps a TRELLIS_IO; use that instead | 15:43 |
| promach3 | Lofty: what do you mean ? I am bit confused | 15:51 |
| *** emeb has joined #yosys | 15:51 | |
| Lofty | Use TRELLIS_IO not BB | 15:52 |
| promach3 | you mean TRELLIS_IO BB_dq (); ? | 15:53 |
| promach3 | Lofty: still same error | 15:53 |
| Lofty | Did you include cells_sim.v in your SBY config? | 15:54 |
| promach3 | which exact cells_sim.v should I download from github ? | 15:54 |
| promach3 | Lofty: | 15:55 |
| Lofty | It's the ECP5 one | 15:55 |
| promach3 | https://github.com/YosysHQ/yosys/blob/master/techlibs/ecp5/cells_sim.v | 15:56 |
| promach3 | Yosys has only limited support for tri-state logic at the moment. (cells_sim.v:401) | 15:57 |
| promach3 | Lofty: smt2: ERROR: Unsupported or unknown directionality on port B of cell ddr3_memory_controller.BB_dqs_n (TRELLIS_IO). | 15:59 |
| Lofty | Then evidently you can't have inout ports in SBY, so you'll need to figure out a way of removing the input buffers | 16:00 |
| promach3 | what ? | 16:00 |
| promach3 | why remove buffer ? | 16:01 |
| promach3 | I need tristate for DDR3 RAM application | 16:01 |
| promach3 | Lofty: | 16:02 |
| Lofty | As I mentioned | 16:03 |
| Lofty | You can't have inout ports | 16:03 |
| Lofty | So you can't have tristate buffers | 16:03 |
| promach3 | thus yosys gave warnings about limited support for tri-state logic | 16:04 |
| Lofty | Yosys does kinda accept tristate logic | 16:04 |
| Lofty | But in this case, it's not really relevant | 16:04 |
| promach3 | but why it failed in my situation ? | 16:04 |
| promach3 | ok, I suppose yosys formal engine does not yet support tri-state logic | 16:05 |
| promach3 | Lofty: | 16:05 |
| Lofty | Well, no | 16:06 |
| promach3 | did I conclude it correctly ? | 16:06 |
| Lofty | In this case, the error is coming from the Yosys smt2 backend | 16:06 |
| Lofty | Where I'm assuming an inout is unrepresentable | 16:07 |
| promach3 | smt2 is related to formal | 16:07 |
| Lofty | Yes, I'm assuming it's a file format | 16:07 |
| promach3 | ok | 16:08 |
| promach3 | so, how do I work around this situation ? | 16:08 |
| promach3 | Lofty: | 16:08 |
| Lofty | ... remove the buffers | 16:08 |
| *** vidbina_ has quit IRC | 16:08 | |
| Lofty | Like I said | 16:08 |
| promach3 | DDR3 require tri-state buffers | 16:08 |
| promach3 | cannot remove tri-state logic | 16:09 |
| Lofty | Yes, but in a formal context you don't need them | 16:09 |
| promach3 | ok, I see | 16:09 |
| promach3 | let me think how to represent tri-state for formal | 16:09 |
| Lofty | Well, you can't. | 16:10 |
| promach3 | Lofty: so, maybe I could assume(some values) for the input direction ? | 16:11 |
| Lofty | if (direction) assert(output condition) else assert(input condition) | 16:11 |
| Lofty | Or something | 16:11 |
| promach3 | cool | 16:11 |
| *** oldtopman has joined #yosys | 18:44 | |
| *** lansiir has quit IRC | 18:44 | |
| *** craigo has quit IRC | 18:45 | |
| cr1901_modern | mwk: Re: the VPR mode in my machxo2 PR... it has become clear talking to symbiflow folks that I didn't actually understand the purpose of the code I was copying, so... oops on my end :P. In the next round of PR, I will remove the VPR mode | 19:03 |
| *** kraiskil has joined #yosys | 20:08 | |
| *** jfcaron has joined #yosys | 20:13 | |
| *** emeb_mac has joined #yosys | 20:42 | |
| *** jfcaron has quit IRC | 20:58 | |
| *** kraiskil has quit IRC | 21:03 | |
| *** vidbina_ has joined #yosys | 21:54 | |
| *** vidbina_ has quit IRC | 23:10 | |
| *** jfcaron has joined #yosys | 23:11 | |
| *** sorear has quit IRC | 23:14 | |
| *** sorear has joined #yosys | 23:17 | |
| *** emeb has quit IRC | 23:54 | |
Generated by irclog2html.py 2.17.2 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!
