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| bjorkintosh | tnt> Basically you use the vendor tools, generate a very simple design, look at the output, tweak a small thing, compare the new output to the previous one, repeat. | 17:57 |
|---|---|---|
| bjorkintosh | how do you know when you've completed such a task? | 17:57 |
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| roamingryan | I think the goal is to understand the function of every single bit in the bitstream. | 18:39 |
| mwk | the goal is to get reasonably full coverage | 18:41 |
| bjorkintosh | sounds like a machine learning(TM) AI (LOL_Buzzword) task! | 18:42 |
| mwk | "every single bit" is unrealistic, mostly due to craploads of test-only bits that are basically useless unless you're factory-testing a bare die | 18:42 |
| bjorkintosh | of course, that's just hand waving. | 18:42 |
| bjorkintosh | mwk, ah. is there a guide line? I have an old xilinx I'd like to make some use of. | 18:43 |
| mwk | no | 18:43 |
| mwk | reversing FPGAs is not a common task | 18:44 |
| mwk | there are no guidelines | 18:44 |
| bjorkintosh | hmm. | 18:44 |
| mwk | and this kind of project takes months or years | 18:45 |
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| bjorkintosh | of course. | 18:48 |
| bjorkintosh | yosys only does verilog now, right? | 18:48 |
| bjorkintosh | no vhdl? | 18:48 |
| mwk | there's a ghdl plugin | 18:48 |
| mwk | which is apparently workable | 18:49 |
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| thoughtpolice | Is the yosys-bot auto-commit currently offline? It hasn't committed an updated tag since Feb 17th. (Just curious and not like, a rush or anything.) | 20:25 |
| mwk | ... I'll ask the responsible people | 20:31 |
| mwk | but yes, it should be commiting | 20:32 |
| mwk | so it presumably broke | 20:32 |
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| thoughtpolice | ty! I maintain a package for Yosys and just like using those tags as the version number for the package. Was curious today and saw it hadn't happened. | 21:35 |
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