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| roamingryan | Are single line `assign` statements the only way to avoid the "assigned in a block at..." warning with Yosys? | 22:47 |
|---|---|---|
| mwk | if you assign something in a block, the proper thing to do in verilog is to declare it as "reg", not "wire" | 22:47 |
| mwk | yosys grudgingly accepts misuse of that, but other tools will flat-out refuse to work | 22:48 |
| roamingryan | I see... even though I want it synthesized as combinatorial logic? | 22:48 |
| mwk | yes | 22:48 |
| mwk | reg/wire distinction is not about combinatorial or synchronous logic, it's about whether it's assigned from a process or not | 22:48 |
| mwk | (verilog is not a particularly well-designed language) | 22:49 |
| roamingryan | Interesting, this is a great to know. | 22:49 |
| roamingryan | So, put differently, one shouldn't scan the input/output ports of a given module and assume that `reg` output pins are registered? | 22:50 |
| mwk | correct | 22:50 |
| roamingryan | That's fun. Thank you for sharing some wisdom. :) | 22:51 |
| mwk | reg output pins can be combinatorial, assigned in a combinatorial process; non-reg output pins can be synchronous if they happen to use assign statements (or submodule instantiations) to bring out the result of a synchronous process defined somewhere deeper | 22:51 |
| roamingryan | Great to know. The module I am implementing requires slightly more logic at an output pin than can be accomodated with a simple ternary assignment operator. I also don't want some sort of nasty nested ternary operator. Hence my question above. Sounds like switching the pin to `reg` and using an `always (*)` block with blocking assignments (`=`) is the way to go. | 22:53 |
| mwk | correct | 22:53 |
| mwk | also please consider using other tools than yosys to check your code, yosys is, uh, good at processing correct code, not so good at diagnosing incorrect code | 22:55 |
| roamingryan | verilator? | 22:55 |
| mwk | yeah, it'd be good to run it through some simulation | 22:55 |
| mwk | verilator or iverilog | 22:55 |
| mwk | whichever you prefer | 22:55 |
| roamingryan | Ok, so far I've been developing purely with yosys and symbiyosys using a "formal first" methodology. I'll get some verilator sims set up in parallel. | 22:56 |
| mwk | that's not a bad plan | 22:57 |
| mwk | but it'd be good to at least run it through a linter | 22:57 |
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| mwk | verilator --lint-only | 22:57 |
| roamingryan | Cool, I'll give that try and see what sort of horrors it reveals. No doubt there will be some! | 22:58 |
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