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| pepijndevos | mwk, I pointed a debugger at that spice.cc warning, but not having much luck with my limited understanding of yosys internals. I'm trying to see which modules it knows about. | 12:26 |
|---|---|---|
| pepijndevos | oh my goodddd I know... | 12:30 |
| pepijndevos | the design->module includes a \ at the start, while the cell->type does not | 12:30 |
| pepijndevos | Is one of the two more correct than the other? Like, should I just slap a blackslash at the front of the cell type and be done with it? | 12:32 |
| pepijndevos | In Verilog, is \foo different from foo? | 12:49 |
| pepijndevos | I seem to recall \foo is a "raw" identifier | 12:50 |
| pepijndevos | So seems there is a mismatch between the $_NORMAL identifiers generated by `synth` and the \$_RAW_ identifiers in simcells.v | 12:52 |
| daveshah | you need to add -icells to read_verilog | 12:52 |
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| pepijndevos | huh | 12:54 |
| pepijndevos | oh okay that works... weird | 12:54 |
| pepijndevos | cool thanks! Now I have a blinky in spice... yay? | 13:02 |
| pepijndevos | hint: https://www.isotel.eu/mixedsim/intro/concept.html | 13:02 |
| tpb | Title: Mixed Signal Simulation Concept ISOTEL (at www.isotel.eu) | 13:02 |
| pepijndevos | bleg, write_spice inserts DC sources, which doesn't work for digital models. | 13:32 |
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| pepijndevos | Would be nice if you could pass to `synth` what kind of flops you want. Seems to be "all of them" rn | 15:14 |
| pepijndevos | I guess just run dfflegalize right after | 15:14 |
| Lofty | pepijndevos: yeah, that's the idea | 15:15 |
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| mwk | *sigh* we had a discussion about it | 15:21 |
| mwk | there's no good way rn | 15:21 |
| mwk | basically `synth` should not be considered a standalone synth flow | 15:21 |
| mwk | and you're supposed to run dfflegalize *and* rerun abc afterwards (because dfflegalize can emit more gates) | 15:22 |
| pepijndevos | hrm | 15:25 |
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| pepijndevos | huh, just realized there isn't a fine LUT cell, so `synth -lut 4` just leaves you with a $lut while `synth` produces fine cells. | 19:45 |
| Lofty | I don't think a fine LUT cell makes any sense | 19:48 |
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| mrec | So acrylic is cutting fine with a single flute upcut bit (which is advertised almost everywhere in the net) | 19:58 |
| mrec | next step m0.5/m0.8 gear cutting | 19:59 |
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