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| awygle | hm, struggling to get nextpnr to accept my edge clock routing between EHXPLLL and EDGECLKSYNCB | 02:16 |
|---|---|---|
| awygle | i'm sure i'm missing some fiddly requirement... | 02:16 |
| awygle | ah i didn't have a DIV attribute | 02:41 |
| awygle | seems like that should work given the default is 2.0. ah well | 02:42 |
| mwk | default parameters on primitives are uhh kind of iffy, given that yosys and nextpnr can and do have differing ideas of those | 02:43 |
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| awygle | i see | 02:56 |
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| mangelis | heh, tried to make 256-long lookup table (4bit out) in verilog, 269 luts | 20:51 |
| mangelis | i wonder if it would be theoretically to get better results, this must be basically a some sort of compression problem | 20:52 |
| mangelis | (269x 3-input luts after synthesis that is) | 20:53 |
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| z0ttel | 256 inputs? | 23:13 |
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