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| mangelis | hi! i wonder if it's possible to use yosys to synthesize verilog to network of generic 3-input 1-output luts? | 14:33 |
|---|---|---|
| mwk | yeah, just `synth -lut 3` | 14:38 |
| mwk | except you'll get a network of LUTs + FFs, which you presumably also need to select | 14:39 |
| mangelis | oh nice | 14:50 |
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| philtor | A yosys discussion has broken out on r/fpga | 19:41 |
| philtor | https://old.reddit.com/r/FPGA/comments/knqvhz/fpga_development_board_for_beginners_programmable/ghrkdk7/ | 19:41 |
| tpb | Title: FieldProgrammable comments on FPGA development board for beginners programmable w/ floss toolchain (at old.reddit.com) | 19:41 |
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