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| tnt | Is there anyway I can force yosys to not use """ assign { io_oeb[37:27], io_oeb[10:0] } = { .... }; """ syntax in write_verilog ? | 19:47 |
|---|---|---|
| tnt | I need to feed the result into a broken tool that doesn't accept that syntax :/ | 19:47 |
| daveshah | tnt: yeah, this was just added as an option to write_verilog because of another broken tool - https://github.com/YosysHQ/yosys/pull/2453 | 20:02 |
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| tnt | daveshah: omg, great timing :D | 20:05 |
| tnt | thanks ! | 20:05 |
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