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| z0ttel | I have an issue with yosys complaining about directionality of a port: | 15:01 |
|---|---|---|
| z0ttel | wire valid_output; assign valid_output = ...; assign out.valid; | 15:01 |
| z0ttel | Oh, sry, there's something missing there | 15:02 |
| z0ttel | wire valid_output; assign valid_output = ...; assign out.valid = valid_output; / / out.valid is an output port. | 15:03 |
| z0ttel | That construct is rewritten to something where the following appears in the write_verilog result: assign valid_output = out.valid; | 15:03 |
| z0ttel | (Which breaks the smt2 backend) | 15:05 |
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| z0ttel | The above description is wrong. Apparently there's a problem with SV interface parameters in the module naming. | 15:53 |
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