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| ArunINT | Hello everyone! | 13:58 |
|---|---|---|
| daveshah | Hi! | 13:58 |
| ArunINT | I have an issue with yosys where vivado compatible verilog i.e (synthesizable in vivado) is throwing "ERROR: Unsupported expression on dynamic range select on signal `$mem2bits$\tlwr_data_buf$test.v" :1086$6'! | 13:59 |
| ArunINT | is this the right place to ask this question | 14:00 |
| daveshah | Yes, let's see the problematic file | 14:00 |
| ArunINT | I cannot share the file as it is NDA bound, but I can try to reproduce this in an example meanwhile here are the details | 14:01 |
| ArunINT | reg [63:0] tlwr_data[2:0]; reg [511:0] tlwr_data_buf[2:0]; reg [2:0] tlwr_burst_cntr[2:0]; tlwr_data[idx] = tlwr_data_buf[idx][{tlwr_burst_cntr[idx], 6'h00} +:64]; | 14:04 |
| ArunINT | idx here is the variable getting incremented in a for loop | 14:04 |
| daveshah | I think that is valid Verilog, so this is a bug | 14:07 |
| daveshah | I don't know the frontend well enough to fix it, so unless someone else here comes along the best bet is to turn that into a minimal example (the problem seems to be an indexing within a part-select) and create a GitHub issue | 14:08 |
| ArunINT | Okay I'll create a github issue, thank you | 14:09 |
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